Takashi Hiroi

Precise visual inspection for LSI wafer patterns using subpixel image alignment

This paper reports on an image processing algorithm and hardware for fast, precise inspection of LSI wafer patterns. In order to detect deep sub-micron defects such as 0.2 /spl mu/m at high speed by grayscale image comparison, we must overcome the sampling errors that inevitably occur between two images during detection. For this purpose, we have developed a subpixel image alignment algorithm that infers the correct sampling position and creates the two resampled images with subpixel accuracy. We have also developed an 8-channel pipelined processor with gate arrays. It has 8/spl times/19,000 gates and can operate at 8/spl times/15 MHz. Evaluation of the system confirmed that the accuracy of the subpixel image alignment was 0.16 pixels or less and that the inspection system could detect 0.18 /spl mu/m defects at a pixel size of 0.25 /spl mu/m for half-micron LSI wafer patterns with an inspection speed of 25 s/cm/sup 2/.<<ETX>>

Pattern alignment method based on consistency among local registration candidates for LSI wafer pattern inspection

This paper reports an image-processing algorithm for robust inspection of LSI wafer patterns using SEM. In order to detect defects in a regular LSI pattern, a pair of long patterns are compared, blocked images are aligned, and defects are judged using the aligned images. The LSI wafer pattern is defined to consist of blank space, fine repetitive patterns, and unique patterns. Distortion of the SEM image is larger than the repetitive pattern pitch, requiring the system to keep track of the alignment in areas without pattern information or in blank space and mitigate the indeterminacy of repetitive patterns. To satisfy these requirements, a two-layer algorithm is proposed. The lower layer calculates registration candidates in each block, and the upper layer determines the correct registration route, i.e. the chain of the correct registration, using candidate information in all the related blocks. Experimental evaluations confirm that most pattern cases can be inspected correctly using the proposed SEM inspection system.

Automated visual inspection for LSI wafer patterns using a derivative-polarity comparison algorithm

Algorithms for visual inspection of LSI wafer multilayer patterns have been developed. These algorithms compare corresponding images of two dies on a wafer. In this paper, two algorithms are proposed. The derivative-polarity comparison algorithm compares the polarities of the first derivatives of two images, and recognizes the regions whose polarities are not matched as positional discrepancies (defects), in order to cope with gray-scale differences caused by pattern thickness errors. The multiple-displacement pattern matching algorithm executes the above polarity comparisons at several positions with images suitably aligned, and determines the common unmatched regions as defective, in order to handle the interlayer- registration errors encountered with multilayer patterns. These algorithms were evaluated experimentally, and it was verified that defects of 0.3 micrometers or more can be reliably detected in multilayer patterns by combining these algorithms.

Robust Defect Detection System Using Double Reference Image Averaging for High Throughput SEM Inspection Tool

This paper reports a defect detection system for a high throughput SEM inspection tool. Although the system has a big advantage compared to optical tools, that is, the ability to detect smaller defects and voltage contrast defects, the cost of ownership (COO) remains high. To enhance COO, throughput enhancement is the critical issue. A larger beam current results in lower image noise and higher throughput. At the same time, the larger the beam current, the lower is the resolution. We suggest a robust defect detection system as a solution to the trade-off between resolution and throughput. The main inspection targets are the voltage contrast (VC) defects on the memory matte. The system judges defects by subtracting a detected image from a reference image, and then determining the defective portion as a larger difference than the pre-determined threshold in the subtracted image. If the noise variation for the two images is a in both cases, the noise in the subtracted image is 1.4 sigma (= radic(sigma2 + sigma2)). We have developed a double reference image averaging (DRIA) system which improves the noise in the reference image by averaging repetitive patterns on the memory matte and noise variation on subtracted image is enhanced to a sigma (= radic(sigma2 + sigma2 )) ideally. This enhancement is equivalent to a two times higher throughput than conventional systems. We also improved the electron beam optics and show that our system throughput is 400 Mpixels per second (pps), which is four times faster than previous systems

Robust defect detection method using reference image averaging for high-throughput SEM wafer pattern inspection system

A wafer pattern inspection system using scanning electron microscopy (SEM) is desirable because electron probing makes it possible to inspect not only surface defects, but also internal electric properties. However, the detection rate of SEM is typically about 100 mega pixels per second (Mpps) due to the effect of shot noise on a signal caused by improving the detection rate. To reduce the cost of ownership of the inspection system, improving throughput of SEM is imperative. Unfortunately, the detection rate remains at 200 Mpps due to physical limitations of the resolution caused by the Coulomb effect and the increasing effect of shot noise. To overcome these limitations, projection electron microscopy systems[1,2] have been proposed. We created a novel image processing method that reliably detects defects images obtained at a 400 Mpps detection rate without increasing the beam current. By using the periodicity of circuit patterns in a memory mat area, the method generates the reference image of a high signal-to-noise ratio by averaging the periodic pattern and detects defects by comparing a defect image with the generated reference image. The theoretical study on the signal-to-noise ratio and the experimental results on the defect detection performance for various sizes of artificial pattern defects are presented.

In-line e-beam inspection with optimized sampling and newly developed ADC

An electron beam inspection is strongly required for HARI to detect contact and via defects that an optical inspection cannot detect. Conventionally, an e-beam inspection system is used as an analytical tool for checking the process margin. Due to its low throughput speed, it has not been used for in-line QC. Therefore, we optimized the inspection area and developed a new auto defect classification (ADC) to use with e-beam inspection as an in-line inspection tool. A 10% interval scan sampling proved able to estimate defect densities. Inspection could be completed within 1 hour. We specifically adapted the developed ADC for use with e-beam inspection because the voltage contrast images were not sufficiently clear so that classifications could not be made with conventional ADC based on defect geometry. The new ADC used the off-pattern area of the defect to discriminate particles from other voltage contrast defects with an accuracy of greater than 90%. Using sampling optimization and the new ADC, we achieved inspection and auto defect review with throughput of less than 1 and one-half hours. We implemented the system as a procedure for product defect QC and proved its effectiveness for in-line e-beam inspection.

Robust and efficient image processing scheme for electron beam LSI wafer pattern inspection

Electron beam-based wafer pattern inspection systems have the major advantage of allowing for the inspection of internal electric properties. However, charge-up of the wafer resulting from the use of an electron beam significantly influences inspection and remains a challenging issue. As an alternative approach to strict charge control, the authors propose a new inspection method that is capable of error-free, one-time inspection for recipe preparation, and which provides high-efficiency defect review and low error ratio inspection. Inspection is carried out at a higher-than-expected sensitivity, and defect candidate images are stored by a defect image analyzer (DIA). After inspection, the stored information contains both actual defects and nuisance defects. The distribution of candidate defects is displayed on a wafer map and the operator reviews the stored images and high-resolution review images on demand in order to check whether defects are true or nuisance defects. If necessary, the operator then adjusts the detection sensitivity and the system re-judges the stored data, displaying the modified wafer map to screen. In this way, the proposed system is robust against sensitivity drift caused by charge-up, and offers efficient, low error ratio inspection.