Yasutaka Toyoda

A new matching engine between design layout and SEM image of semiconductor device

Optical proximity correction (OPC) plays a vital role in the lithography process development of current semiconductor devices. OPC is utilized to achieve the ideal pattern shape because of the limitations of optical resolution. However, the lithography process design has become increasingly more complex due to the abundant use of OPC features. Hence, metrology requests for CD-SEM have also become more complex and diverse in order to characterize the critical OPC models. The number of measurement points for OPC model evaluation has increased to several hundred points per layer, and metrology requests for realized pattern shapes on the wafer are no longer simple one-dimensional measurements. Metrology requests include not only the traditional line width measurements, but also edge placement error (EPE) and corner rounding to identify line end shortening. Several researchers have proposed using the design layout as a template instead of the SEM image for the recipe creation of CD-SEM and EPE measurement. However, it is very difficult to achieve good matching results between the design layout and the SEM image in practical processing times. Hitachi High-Technologies has developed a robust and quick matching engine between the design layout and SEM image bitmap. The new system, incorporating this new matching engine, can automatically create a practical recipe from the coordinate information of measurement point and the design layout information, such as GDSII. As a result, the new system can vastly reduce the amount of time and number of operations required to generate a several-hundred point CD-SEM recipe for OPC evaluation. This study demonstrates the capability and presents evaluation results of this new matching engine. This new capability has proven to be a viable solution for OPC evaluation, and its efficiency will allow for quicker information turns between design and manufacturing.

New method of Contour based mask shape compiler

We have developed a new method of accurately profiling a mask shape by utilizing a Mask CD-SEM. The method is intended to realize high accuracy, stability and reproducibility of the Mask CD-SEM adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD measurement. In comparison with a conventional image processing method for contour profiling, it is possible to create the profiles with much higher accuracy which is comparable with CD-SEM for semiconductor device CD measurement. In this report, we will introduce the algorithm in general, the experimental results and the application in practice. As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC (Optical Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the view point of DFM (Design for Manufacturability), a dramatic increase of data processing cost for advanced MDP (Mask Data Preparation) for instance and surge of mask making cost have become a big concern to the device manufacturers. In a sense, it is a trade-off between the high accuracy RET and the mask production cost, while it gives a significant impact on the semiconductor market centered around the mask business. To cope with the problem, we propose the best method for a DFM solution in which two dimensional data are extracted for an error free practical simulation by precise reproduction of a real mask shape in addition to the mask data simulation. The flow centering around the design data is fully automated and provides an environment where optimization and verification for fully automated model calibration with much less error is available. It also allows complete consolidation of input and output functions with an EDA system by constructing a design data oriented system structure. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

SEM-contour shape analysis method for advanced semiconductor devices

The new measuring method that we developed executes a contour shape analysis that is based on the pattern edge information from a SEM image. This analysis helps to create a highly precise quantification of every circuit pattern shape by comparing the contour extracted from the SEM image using a CD measurement algorithm and the ideal circuit pattern. The developed method, in the next phase, can generate four shape indices by using the analysis mass measurement data. When the shape index measured using the developed method is compared the CD, the difference of the shape index and the CD is negligibly small for the quantification of the circuit pattern shape. In addition, when the 2D patterns on a FEM wafer are measured using the developed method, the tendency for shape deformations is precisely caught by the four shape indices. This new method and the evaluation results will be presented in detail in this paper.

Integration of mask and silicon metrology in DFM

We have developed a highly integrated method of mask and silicon metrology. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. We have inspected the high accuracy, stability and reproducibility in the experiments of integration. The accuracy is comparable with that of the mask and silicon CD-SEM metrology. In this report, we introduce the experimental results and the application. As shrinkage of design rule for semiconductor device advances, OPC (Optical Proximity Correction) goes aggressively dense in RET (Resolution Enhancement Technology). However, from the view point of DFM (Design for Manufacturability), the cost of data process for advanced MDP (Mask Data Preparation) and mask producing is a problem. Such trade-off between RET and mask producing is a big issue in semiconductor market especially in mask business. Seeing silicon device production process, information sharing is not completely organized between design section and production section. Design data created with OPC and MDP should be linked to process control on production. But design data and process control data are optimized independently. Thus, we provided a solution of DFM: advanced integration of mask metrology and silicon metrology. The system we propose here is composed of followings. 1) Design based recipe creation: Specify patterns on the design data for metrology. This step is fully automated since they are interfaced with hot spot coordinate information detected by various verification methods. 2) Design based image acquisition: Acquire the images of mask and silicon automatically by a recipe based on the pattern design of CD-SEM.It is a robust automated step because a wide range of design data is used for the image acquisition. 3) Contour profiling and GDS data generation: An image profiling process is applied to the acquired image based on the profiling method of the field proven CD metrology algorithm. The detected edges are then converted to GDSII format, which is a standard format for a design data, and utilized for various DFM systems such as simulation. Namely, by integrating pattern shapes of mask and silicon formed during a manufacturing process into GDSII format, it makes it possible to bridge highly accurate pattern profile information over to the design field of various EDA systems. These are fully integrated into design data and automated. Bi-directional cross probing between mask data and process control data is allowed by linking them. This method is a solution for total optimization that covers Design, MDP, mask production and silicon device producing. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

SEM-contour shape analysis based on circuit structure for advanced systematic defect inspection

We have developed a practicable measurement technique that can help to achieve reliable inspections for systematic defects in advanced semiconductor devices. Systematic defects occurring in the design and mask processes are a dominant component of integrated circuit yield loss in nano-scaled technologies. Therefore, it is essential to ensure systematic defects are detected at an early stage of wafer fabrication. In the past, printed pattern shapes have been evaluated by human eyes or by taking manual critical dimension (CD) measurements. However, these operations are sometimes unstable and inaccurate. Last year, we proposed a new technique for taking measurements by using a SEM contour [1]. This technique enables a highly precise quantification of various complex 2D shaped patterns by comparing a contour extracted from a SEM image using a CD measurement algorithm and an ideal pattern. We improved this technique to enable the carrying out of inspections suitable for every pattern structure required for minimizing the process margin. This technique quantifies a pattern shape of a target-layer pattern using information on a multi-layered circuit structure. This enabled it to confirm the existence of a critical defect in a circuit connecting upper/lower-layers. This paper describes the improved technique and the evaluation results obtained in evaluating it in detail.

Contour-based metrology for complex 2D shaped patterns printed by multiple-patterning process

We developed a new measurement method enabling to quantitatively and accurately evaluate 2D pattern shapes, which becomes critical in patterning control of Metal layer patterns transferred by Litho-Etch-Litho-Etch (LELE) process. In LELE, a split patterning of a Metal-A (MA) layer and a Metal-B (MB) layer makes patterning control more challenging. Hence, it is essential to evaluate the shape of transferred patterns after final etching in order to verify that the patterning control of MA and MB layer patterns is performed within an allowable budget. For this, our Pattern Shape Quantification (PSQ) method [1][2][3], which enables to measure dimensional difference of the transferred pattern shape from their target-design, is an effective metrology. Patterns transferred through a LELE process contain the effects of two types of shape modifications. The first is the fidelity of the individual pattern shapes (e.g. pattern-end pull-back or push-out) whose determinative factors are adopted design (e.g. OPC and SRAF), process condition (of e.g. lithography and etching), etc. The second is the shift in position between MA and MB patterns induced by Pattern Placement Error (PPE) of MB with respect to MA. That means that the edge-placement errors (EPE) in the final pattern are not only due to the fidelity of the transferred pattern shape, but are also impacted by the PPE. Also, a space between MA and MB patterns will be affected by the PPE as well. A failure to maintain a required minimum space between patterns could lead to a leak-current between patterns (and hence directly affect device performance), so it is important that the PPE can be measured accurately. Therefore, we developed a method to measure local PPE in actual device patterns, from CD-SEM images, that also outputs a pattern-contour in which this PPE has been removed. Utilizing such a pattern-contour into the PSQ method enables to quantitatively determine the fidelity of transferred pattern shape solely induced by the 1st shape modification, while providing PPE data from the device patterns themselves. We believe that a high-quality patterning control (by e.g. optimization of process condition) of MA and MB can be performed only by using such a measurement result. This paper demonstrates and discusses the capability and effectiveness of our newly developed method.

New method of 2-dimensional metrology using mask contouring

We have developed a new method of accurately profiling and measuring of a mask shape by utilizing a Mask CD-SEM. The method is intended to realize high accuracy, stability and reproducibility of the Mask CD-SEM adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD measurement. In comparison with a conventional image processing method for contour profiling, this edge detection method is possible to create the profiles with much higher accuracy which is comparable with CD-SEM for semiconductor device CD measurement. This method realizes two-dimensional metrology for refined pattern that had been difficult to measure conventionally by utilizing high precision contour profile. In this report, we will introduce the algorithm in general, the experimental results and the application in practice. As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC (Optical Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the view point of DFM (Design for Manufacturability), a dramatic increase of data processing cost for advanced MDP (Mask Data Preparation) for instance and surge of mask making cost have become a big concern to the device manufacturers. This is to say, demands for quality is becoming strenuous because of enormous quantity of data growth with increasing of refined pattern on photo mask manufacture. In the result, massive amount of simulated error occurs on mask inspection that causes lengthening of mask production and inspection period, cost increasing, and long delivery time. In a sense, it is a trade-off between the high accuracy RET and the mask production cost, while it gives a significant impact on the semiconductor market centered around the mask business. To cope with the problem, we propose the best method of a DFM solution using two-dimensional metrology for refined pattern.

Focus measurement using SEM image analysis of circuit pattern

We have developed a new focus measurement method based on analyzing SEM images that can help to control a scanner. In advanced semiconductor fabrication, rigorous focus control of the scanner has been required because focus error causes a defect. Therefore, it is essential to ensure focus error are detected at wafer fabrication. In the past, the focus has been measured using test patterns made outside of the chip by optical metrology system. Thus, present focus metrology system can’t measure the focus of an arbitrary point in the chip. The new method enables a highly precise focus measurement of the arbitrary point of the chip based on a focus plane of a reference scanner. The method estimates the focus amount by analyzing side wall shapes of circuit patterns of SEM images. Side wall shapes are quantified using multisliced contours extracted from SEM-images high accuracy. By using this method, it is possible to measure the focus of the arbitrary circuit pattern area of the chip without a test pattern. We believe the method can contribute to control the scanner and to detect hot spots which appear by focus error. This new method and the evaluation results will be presented in detail in this paper.

Consideration of correlativity between litho and etching shape

We developed an effective method for evaluating the correlation of shape of Litho and Etching pattern. The purpose of this method, makes the relations of the shape after that is the etching pattern an index in wafer same as a pattern shape on wafer made by a lithography process. Therefore, this method measures the characteristic of the shape of the wafer pattern by the lithography process and can predict the hotspot pattern shape by the etching process. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used wafer CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and lithography management, and this has a big impact on the semiconductor market that centers on the semiconductor business. 2-dimensional shape of wafer quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. In this study, we conducted experiments for correlation method of the pattern (Measurement Based Contouring) as two-dimensional litho and etch evaluation technique. That is, observation of the identical position of a litho and etch was considered. It is possible to analyze variability of the edge of the same position with high precision.

Study of shape evaluation for mask and silicon using large field of view

We have developed a highly integrated method of mask and silicon metrology. The aim of this integration is evaluating the performance of the silicon corresponding to Hotspot on a mask. It can use the mask shape of a large field, besides. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and mask manufacture, and this has a big impact on the semiconductor market that centers on the mask business. As an optimal solution to these issues, we provide a DFM solution that extracts 2-dimensional data for a more realistic and error-free simulation by reproducing accurately the contour of the actual mask, in addition to the simulation results from the mask data. On the other hand, there is roughness in the silicon form made from a mass-production line. Moreover, there is variation in the silicon form. For this reason, quantification of silicon form is important, in order to estimate the performance of a pattern. In order to quantify, the same form is equalized in two dimensions. And the method of evaluating based on the form is popular. In this study, we conducted experiments for averaging method of the pattern (Measurement Based Contouring) as two-dimensional mask and silicon evaluation technique. That is, observation of the identical position of a mask and a silicon was considered. The result proved its detection accuracy and reliability of variability on two-dimensional pattern (mask and silicon) and is adaptable to following fields of mask quality management. •Discrimination of nuisance defects for fine pattern. •Determination of two-dimensional variability of pattern. •Verification of the performance of the pattern of various kinds of Hotspots. In this report, we introduce the experimental results and the application. We expect that the mask measurement and the shape control on mask production will make a huge contribution to mask yield-enhancement and that the DFM solution for mask quality control process will become much more important technology than ever. It is very important to observe the form of the same location of Design, Mask, and Silicon in such a viewpoint. And we report it about algorithm of the image composition in Large Field.