Fumiki Kato

Investigation of low-temperature deposition high-uniformity coverage Parylene-HT as a dielectric layer for 3D interconnection

Polymer low-k materials have been considered in literature to meet the requirements of lowering the dielectric constant of the dielectric layer to decrease the problem of signal delay, lower power consumption, and reduce cross-talk between the neighboring paths, as well as, lower the fabrication temperature budget. In this paper, the feasibility of using Parylene-HT as a low-temperature deposition intelever dielectric in 3D interconnection is investigated and the results are presented. In particular, the diffusivities of Cu in room temperature deposited high-uniformity coverage Parylene-HT at 250 oC and 350 oC are evaluated to be 5.7E-18 cm2/s and 1.3E-16 cm2/s respectively, by dynamic secondary ion mass spectrometry (D-SIMS) technique. In addition, the capability of embedding Parylene-HT in through-Si-via (TSV) fabrication process through the demonstration of 36-μm-diameter 100-μm-depth copper-filled TSVs using Parylene-HT as a liner, are reported.

A novel method of hotspot temperature reduction for a 3D stacked CMOS IC chip device fabricated on an ultrathin substrate

A high-performance thermal management method for three-dimensional integrated circuit (IC) integration has been developed for use in conjunction with a three-dimensional (3D) large-scale integration (LSI) technology. By depositing a 10 µm thick high thermal conductivity (HTC) film consisting of 1680 alternating layers of silicon and graphite nano-films directly onto the backside of a Si substrate via an automatic sequencing sputtering method, reduction in the transient hotspot temperature in a thin-substrate CMOS IC chip is achieved. It is shown that this novel HTC film is able to overcome the thermal problems associated with thin substrates and allow the cooling of stacked ICs. In the work described in this paper, we demonstrated the performance of the HTC using a 100 µm thick substrate IC chip consisting of a complementary metal-oxide semiconductor (CMOS) ring oscillator circuit film. Our experimental results, which were confirmed in simulation, reveal a 28% reduction in the hotspot temperature rise owing to the presence of the HTC film. This technology is applicable to future developments in the 3D ultrathin substrate LSI chip stacking technology utilizing through-silicon vias (TSVs) and micro-bumps.

Fabrication and electrical characterization of Parylene-HT liner bottom-up copper filled through silicon via (TSV)

In this study, Parylene-HT, the newest commercially available parylene with the lowest dielectric constant and highest temperature tolerance within all the series, was investigated as insulation/liner in the application of through-silicon-via (TSV). Bottom-up copper filled TSV with 1 μm Parylene-HT insulator was realized on a 100 μm-thick Si wafer through via etching, parylene vapor deposition, and electroplating processes. The fabrication process on the 36 μm diameter TSVs, are reported here, as well as their electrical properties, including DC leakage and capacitance.

Flip-chip bonding alignment accuracy enhancement using self-aligned interconnection elements to realize low-temperature construction of ultrafine-pitch copper bump interconnections

In this paper, the integration accuracy of conventional flipchip bonding is effectively enhanced by means of automatically maintaining the alignment between the chip and substrate during the time that offsets may take place, i.e., bonding conditions applying period. The conventional bonding bump and pad elements have been appropriately modified to construct a concave-convex pair, i.e., self-aligned interconnection elements (SIEs). By this way, the post-bond offsets are determined by the SIEs, aiming at highly reproducible sub-micron range bonding precision. Moreover, because the post-bond offsets are guaranteed by the SIEs, ultrasonic assisted technique can be applied to make reliable bonds at acceptably low temperatures, while still maintaining the integration accuracy. Ultrafine-pitch (i.e. down to 10 μm) copper bump interconnections were realized using the proposed integration approach.

15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications

In this paper, we report the development of reliable fine-pitch micro bump interconnections that used a high-precision room-temperature bonding approach. The accuracy of the bonding process is improved by modifying conventional bump/planar-bonding-pad interconnections to form self-aligned micro bumps/truncated inverted pyramid (TIP) bonding pads, i.e., misalignment self-correction elements (MSCEs). Thermosonic flip-chip bonding (FCB) is utilized to form reliable bonds between these MSCEs at acceptable low temperatures. By applying the proposed bonding approach, the demonstration of fine-pitch Cu bump to Au bonding pad interconnects chip stacking has been realized. Microstructure analyses reveal that 15-µm-pitch micro bump joints are fabricated at room temperature.

250 °C-Operated sandwich-structured all-SiC power module

The operation of a sandwich structured all-SiC power module is demonstrated at 250 °C. The power module was designed by considering two thermal deformation issues. Thermally induced bending of the SiN-AMC substrates is reduced by introducing symmetrical Cu wiring patterns on both sides of the SiN ceramic plate. The concentration of stress located in the gate joint material is drastically reduced by introducing a trench structure in the Cu wiring layer of the gate interconnection. A double pulse test at a high temperature is carried out. At 250 °C, the all-SiC sandwich-structured power module was successfully operate at 600 V and 15 A. The maximum switching transient speed (dV/dt) of turn-on and turn-off are observed 10.7 and 12.1 V/ns, respectively.

Modified thermosonic flip-chip bonding based on electroplated Cu microbumps and concave pads for high-precision low-temperature assembly applications

Thermosonic flip-chip bonding (TS-FCB) is known as a technique suitable for low-temperature bonding and has been used in many integration applications. In this paper, a modified TS-FCB based on microbumps and concave pads, is presented. Electroplated Cu microbumps, and etched invert-pyramid-shape bonding pads are used to enhance the bonding accuracy of the conventional TS-FCB technique. Experimental validation of the bonding approach is conducted. Reliable bonds, with significant increase in the post-bond accuracy, i.e. within 1 μm range in in-plane offsets, are obtained at 120°C using the proposed bonding approach. These achievements illustrate the ability to use this approach for high-precision low-temperature converging applications.

Wide bus chip-to-chip interconnection technology using fine pitch bump joint array for 3D LSI chip stacking

We have developed a fabrication technology of fine-pitch cone shape Au bump array using nanoparticle deposition method for 3D LSI chip stacking. 1024-bit wide bus chip-to-chip interconnection circuit called Cool Interconnect has been also developed using fine-pitch bump joint array technology and precise flip chip bonding technology. Such a wide bus chip-to-chip interconnection is suitable instead of on-chip bus interconnection in multi-core architecture LSI system in order to achieve low power operation. We propose a testing approach to confirm the chip-to-chip interconnect electrical performance using scan path method and JTAG test method in 3D LSI chip stacking system. The preliminary data transmitting experiment of Cool Interconnect using designed, fabricated, and flip-chip stacked test LSI chips was successfully done under low power consumption with clock frequency of 50MHz.

Copper-Filled Through-Silicon Vias With Parylene-HT Liner

Organic low-k materials have been considered in the literature for satisfying the requirements of lowering the dielectric constant of the dielectric layer to decrease the problem of signal delay, lower power consumption, and to reduce cross talk between the neighboring paths, and lowering the fabrication temperature budget. In this paper, the feasibility of using Parylene-HT as a low-temperature deposition, high-uniformity coverage low-dielectric liner for copper-filled through-silicon vias (TSVs) in 3-D integration is investigated. In particular, the capability of embedding Parylene-HT in via-last fabrication process is validated through the demonstration of 100-μm-depth bottom-up copper-filled TSVs. TSVs with Parylene-HT as a liner were realized through vias etching, parylene vapor deposition, and copper electroplating processes. The Parylene-HT deposition and copper electroplating processes were implemented at room temperature, such that thermal-related issue would be avoided and device reliability would be enhanced. The insulation function of the Parylene-HT liner of the fabricated TSVs was characterized. Capacitance of 0.164 pF/TSV and leakage current density of 22 pA/cm2 at a field of 0.25 MV/cm were obtained through the measurement of the TSV arrays. The obtained results reveal the possibility of using such a high potential parylene in low-temperature budget 3-D integration applications.

High-precision heterogeneous integration based on flip-chip bonding using misalignment self-correction elements

A bonding technique, capable of sub-micron and finer alignment accuracy, has been developed for electronics-optics heterogeneous integration applications. The technique is based on the principle of misalignment self-correction using bump (convex) and hollow (concave) elements, to align one die (i.e. a chip) to another one (i.e. a substrate) during the stacking process. Conductive hollow pad and Au cone bump elements were micro machined on silicon wafers using wet anisotropic (TMAH) etching and deposition processes, respectively, and the bonding technique was examined. Repeatable bonding accuracy on the order of less than 100 nm was obtained through experimental investigation.