Shunsuke Nemoto

15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications

In this paper, we report the development of reliable fine-pitch micro bump interconnections that used a high-precision room-temperature bonding approach. The accuracy of the bonding process is improved by modifying conventional bump/planar-bonding-pad interconnections to form self-aligned micro bumps/truncated inverted pyramid (TIP) bonding pads, i.e., misalignment self-correction elements (MSCEs). Thermosonic flip-chip bonding (FCB) is utilized to form reliable bonds between these MSCEs at acceptable low temperatures. By applying the proposed bonding approach, the demonstration of fine-pitch Cu bump to Au bonding pad interconnects chip stacking has been realized. Microstructure analyses reveal that 15-µm-pitch micro bump joints are fabricated at room temperature.

Modified thermosonic flip-chip bonding based on electroplated Cu microbumps and concave pads for high-precision low-temperature assembly applications

Thermosonic flip-chip bonding (TS-FCB) is known as a technique suitable for low-temperature bonding and has been used in many integration applications. In this paper, a modified TS-FCB based on microbumps and concave pads, is presented. Electroplated Cu microbumps, and etched invert-pyramid-shape bonding pads are used to enhance the bonding accuracy of the conventional TS-FCB technique. Experimental validation of the bonding approach is conducted. Reliable bonds, with significant increase in the post-bond accuracy, i.e. within 1 μm range in in-plane offsets, are obtained at 120°C using the proposed bonding approach. These achievements illustrate the ability to use this approach for high-precision low-temperature converging applications.

Wide bus chip-to-chip interconnection technology using fine pitch bump joint array for 3D LSI chip stacking

We have developed a fabrication technology of fine-pitch cone shape Au bump array using nanoparticle deposition method for 3D LSI chip stacking. 1024-bit wide bus chip-to-chip interconnection circuit called Cool Interconnect has been also developed using fine-pitch bump joint array technology and precise flip chip bonding technology. Such a wide bus chip-to-chip interconnection is suitable instead of on-chip bus interconnection in multi-core architecture LSI system in order to achieve low power operation. We propose a testing approach to confirm the chip-to-chip interconnect electrical performance using scan path method and JTAG test method in 3D LSI chip stacking system. The preliminary data transmitting experiment of Cool Interconnect using designed, fabricated, and flip-chip stacked test LSI chips was successfully done under low power consumption with clock frequency of 50MHz.

Development of micro bump joints fabrication process using cone shape Au bumps for 3D LSI chip stacking

3D LSI chip stacking technology have been developed using cone shape Au micro bumps fabricated by nanoparticle deposition method. The cone shape bumps with less than 10 um diameter are suitable for a thermocompression bump joint process with low temperature and low load force. High yield micro bump joints can be obtained. In this study, the property evaluation of the cone shape bumps, and the cone shape bump joints were investigated in details. The collapsed bump height and the electrical resistance can be controlled by compression force. The low resistance (average 8.6 mΩ) bump joint with a 10 μm diameter cone shape Au bump was successfully achieved.

New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking

3D LSI chip stacking technology has been developed in AIST using cone shape micro bumps fabricated by nanoparticle deposition method. The cone shape bumps are suitable for a thermocompression bump joint process with low temperature and low load force, where the bumps are easy to collapse with loading due to the pointed structure. High yield micro bump joints can be obtained. The three dimensional measurement of the cone shape bumps can be done using laser scanning microscope or scanning electron (ion) beam microscope (SEM, SIM). It takes much long time to get the precise three dimensional measurement data. It is not suitable for a mass production inspection test. The highly efficient measurement technique is required for this purpose. We propose a new optical three dimensional structure measurement technique using optical microscopes with CCD cameras or line sensors. In this technique, the dimensional measurement of bumps is done by image processing with three images captured by three microscopes, where one microscope is for a top view and the other two are for slanting views from two directionals which counter.

High-precision heterogeneous integration based on flip-chip bonding using misalignment self-correction elements

A bonding technique, capable of sub-micron and finer alignment accuracy, has been developed for electronics-optics heterogeneous integration applications. The technique is based on the principle of misalignment self-correction using bump (convex) and hollow (concave) elements, to align one die (i.e. a chip) to another one (i.e. a substrate) during the stacking process. Conductive hollow pad and Au cone bump elements were micro machined on silicon wafers using wet anisotropic (TMAH) etching and deposition processes, respectively, and the bonding technique was examined. Repeatable bonding accuracy on the order of less than 100 nm was obtained through experimental investigation.

Investigation into the thermal effects of thinning stacked dies in three-dimensional integrated circuits

In three-dimensional integrated circuits (3DICs) aggressive wafer-thinning can lead to large thermal gradient, including spikes in individual device temperatures. In a non-thinned circuit the large bulk silicon wafer on which devices are built works as a very good thermal conductor, enabling heat to diffuse laterally. In this paper we experimentally examine the thermal resistance from an active heater to the heatsink in a two-tier bump-bonded 3D stacked system. A simplified structure is introduced to enable such measurements without the time and cost associated with the full fabrication of such a system. Die thinning is seen to have a pronounced effect on the thermal response. Thinning the top tier from 725 μm to 20 μm results in a nearly 7 times increase in the thermal resistance from heater to heatsink.

Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging

The high-speed signal transmission characteristics of high density flip-chip interconnect with micro Au bumps were investigated. A test element group device and substrate was designed and fabricated to measure the properties of the high density interconnect structure. The test chip and substrate had Cu wires patterned to create a controlled impedance coplanar waveguide (CPW) transmission line in order to test the highspeed signal transmission properties. The characteristic impedance and S-parameters (S21, S11) of the flip-chip bonded test chip and substrate was measured. 50-ohm CPWs with two micro bump joints and underfill were successfully fabricated. In this work we have presented a method for designing specific impedance and high frequency properties on Si substrates in the presence of underfill and flip-chip bonded circuits.

Developing a leading practical application for 3D IC chip stacking technology: How to progress from fundamental technology to application technology

−1− Synthesiology English edition Vol.9 No.1 pp.1-15 (Jun. 2016) IC technologies, and the attempt to increase the integration density seemed to face the limit. The three-dimensional IC chip stacking technology whereby the IC devices are stacked vertically and packaged is one of the solutions, and expectation for it is rising recently as a technology for semiconductor device stacking that enables the increase of integration density for semiconductor ICs. Therefore, we established the fundamental technology for high-density high-integration electronic hardware construction required for 3D IC chip stacking, and we are working on the R&D of the application phase to create the flow of application system development, while engaging in technical support of massproduction technology that, in practice, should be undertaken by leading companies.

High-speed optical three dimensional measurement method for micro bump inspection in 3D LSI chip stacking technology

3D LSI chip stacking technology has been developed in AIST using cone shape micro bumps fabricated by nanoparticle deposition method. The cone shape bumps are suitable for a thermocompression bump joint process with low temperature and low load force, where the bumps are easy to collapse with loading due to the pointed structure. High yield micro bump joints can be obtained. The three dimensional measurement of the cone shape bumps can be done using laser scanning microscope or scanning electron beam microscope. It is not suitable for a mass production inspection test. We have proposed a new optical three dimensional structure measurement technique using optical microscopes with image sensors or line sensors. We developed recently a high-speed optical three dimensional measurement system using specially manufactured optical microscopes with high-speed 8192-pixel line sensors, which can be used for a mass-production process line. Blue laser diffused illumination was equipped to obtain a high resolution. The cone shape bump height measurement with standard deviation less than 0.3 μm was confirmed. The high-speed wafer measurement was demonstrated using 10 μm diameter Cu pillar bumps.