Fumio Murabayashi

A BiCMOS logic gate with positive feedback

It is noted that, as BiCMOS process technology is refined, the supply voltage must be reduced due to the lower endurance voltage of the devices and the larger power dissipation of the LSI chips. As the MOS drain current decreases with supply voltage, the base current from the MOS in a BiCMOS logic gate should then be sufficient for high-speed switching. Also, as the threshold voltage of the MOS becomes lower, a full logic swing function is necessary, even for BiCMOS gates, to ensure that a DC current does not flow in the next gate. These problems were solved with a BiCMOS logic gate with positive feedback, which was fabricated using a 0.5- mu m BiCMOS device and applied to a channelless gate array for a high-speed processor. Characteristics of the proposed logic gates are summarized. Experimental t/sub pd/ and P/sub d/ versus C/sub L/ characteristics for the three-input NAND at 4-V supply voltage are shown.<<ETX>>

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Novel 2.5 V CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 200 MHz superscalar RISC processor. The NTP circuit has two advantages: high noise immunity and high speed. Floating point operations can be executed in a two cycle latency using the high speed NTP circuit. The leakless buffer circuit with NMOS transmission gate in 128 floating point registers makes possible both high integration and low power dissipation, since the circuit causes no leak current without precharging the number of read lines. The processor makes use of 0.3 /spl mu/m CMOS technology with a 2.5 V power supply and four metal layers. The floating point macrocell has 380 thousand transistors and dissipates 350 mW at 200 MHz. The peak performance of the floating point macrocell is 400 MFLOPS.

A 120-MHz BiCMOS superscalar RISC processor

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm/spl times/16.5 mm, and utilizes 3.3 V/0.5 /spl mu/m BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design. >

A feedback-type BiCMOS logic gate

The authors report on the development of a feedback-type BiCMOS logic gate using a 0.5- mu m BiCMOS technology. The propagation delay time of a three-input NAND gate with a 0.93-pF load is 245 and 290 ps at a supply voltage of 4.5 and 4 V, respectively. These values are about 1.4-1.2 times better than the 0.8- mu m BiCMOS gate operating at 5 V. A power dissipation of 0.4 mW was obtained with a 0.93-pF load, 4-V supply voltage, and 140-MHz operation. The power dissipation is comparable to that of a CMOS gate. >

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB cache, and contains 2.8 million transistors. The processor executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense amplifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are applied to the processor. The processor with the proposed BiCMOS circuits has a 11%-47% shorter delay time advantage over a CMOS microprocessor. >

A 0.5 amu;m BiCMOS channelless gate array

A BiCMOS channelless gate array using 0.5-μm BiCMOS technology is described. To improve the speed and density of the gate array, a novel feedback-type BiCMOS circuit and the channelless architecture were adopted. The plane-type gate array has 54 K cells and can construct a three-input NAND or NOR gate using one of them. The array realizes the high utilization ratio of basic cells using a four-metal-layer wiring technique. If macrocells are used, the density of the chip becomes more than twice that of a plane-type gate array. The gate delay time of 220 ps was simulated using a feedback-type BiCMOS two-input NAND circuit and 0.5-μm BiCMOS devices with a 4-V power supply. This high-performance BiCMOS channelless gate array can be applied to high-speed computers

A programmable sensor signal conditioning LSI

A programmable sensor signal conditioning LSI has a programmable interface circuit to input various signals and has a wide signal range from 10 mV to 2 V. The LSI can calibrate errors of various sensors transfer within 0.5% accuracy in a wide signal range. The signal conditioning LSI has three main modules, that is a sigma-delta AD-converter, a high reliability EPROM, and a 16 bit signal conditioning DSP. The sigma-delta AD-converter has a programmable interface and 10 /spl mu/V minimum resolution. Information determining the input signal range and calibration data are stored in a high reliability EPROM which has a redundant cell architecture. These modules have been integrated in a 0.8 /spl mu/m CMOS process and the chip is 4.3 mm/spl times/4.7 mm.

3.3 V, novel circuit techniques for a 2.8-million-transistor BiCMOS RISC processor

3.3-V, high-speed circuit techniques, including a 0.6-ns single-ended common-base sense circuit, a 0.5-ns 22-b comparator circuit, and a 0.7-ns 3-input adder circuit, are applied to a 2.8-million-transistor RISC (reduced instruction set computer) microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS 3.3-V 4-metal-layer technology. The chip includes a 240-MFLOPS (million floating point operations per second) double-precision floating-point unit and a 24-kByte cache, and dissipates 17 W at 120 MHz.

A 400MHz 160-word &#215; 64-bit 14-port floating-point register file macrocell for a superscalar RISC processor

A 400MHz 160-word × 64-bit 14-port floating-point register file for a superscalar RISC processor is presented. A large number of registers makes it possible to hide the long access latency of the main memory, and improves the performance of a processor by over double. A line boost circuit and a precharge circuit are successfully applied to the register file to realize 1.4ns read access. The register file makes use of 0.25µm CMOS technology with a 1.8V power supply. It has 856K transistors and dissipates 2.5W at 400MHz.