Tatsumi Yamauchi

1.3- mu m CMOS/bipolar standard cell library for VLSI computers

The CMOS/bipolar standard cell library has been enhanced from 2 to 1.3 mu m for application to VLSI computers, such as 32-bit supermini- and microcomputers. This library has macrocells such as a 256-kb/8.4-ns ROM, 32-bit/4.5-ns carry propagation circuits for a 32-bit ALU, 4-kbyte/17-ns cache memory including an address translation function, and a 64-bit/37-ns multiplier. High integration density is obtained by using CMOS-based circuits and fast operation is achieved by using CMOS/bipolar sense circuits and drivers. In the cache memory, a functional sense amplifier, in which a conventional sense amplifier and a comparator are merged, is used. How to combine CMOS and bipolar devices in the macrocells along with application of the library to the VLSI computers is discussed. >

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Novel 2.5 V CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 200 MHz superscalar RISC processor. The NTP circuit has two advantages: high noise immunity and high speed. Floating point operations can be executed in a two cycle latency using the high speed NTP circuit. The leakless buffer circuit with NMOS transmission gate in 128 floating point registers makes possible both high integration and low power dissipation, since the circuit causes no leak current without precharging the number of read lines. The processor makes use of 0.3 /spl mu/m CMOS technology with a 2.5 V power supply and four metal layers. The floating point macrocell has 380 thousand transistors and dissipates 350 mW at 200 MHz. The peak performance of the floating point macrocell is 400 MFLOPS.

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB cache, and contains 2.8 million transistors. The processor executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense amplifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are applied to the processor. The processor with the proposed BiCMOS circuits has a 11%-47% shorter delay time advantage over a CMOS microprocessor. >

A programmable sensor signal conditioning LSI

A programmable sensor signal conditioning LSI has a programmable interface circuit to input various signals and has a wide signal range from 10 mV to 2 V. The LSI can calibrate errors of various sensors transfer within 0.5% accuracy in a wide signal range. The signal conditioning LSI has three main modules, that is a sigma-delta AD-converter, a high reliability EPROM, and a 16 bit signal conditioning DSP. The sigma-delta AD-converter has a programmable interface and 10 /spl mu/V minimum resolution. Information determining the input signal range and calibration data are stored in a high reliability EPROM which has a redundant cell architecture. These modules have been integrated in a 0.8 /spl mu/m CMOS process and the chip is 4.3 mm/spl times/4.7 mm.

A 6-ns 256-kbit BiCMOS TTL SRAM

A 6-ns 64K*4-b BiCMOS, transistor-transistor logic (TTL)-I/O SRAM has been developed. Fast access time is due to the combination of innovative circuits and a double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The novel circuits include a reduced-stage BiCMOS decoder and a current-sense-type address transition detection circuit. The chip size is 4.25 mm*10 mm. Simulated internal delay time components of a critical path of the decoder are shown. Address access time is 6 ns at T/sub a/=25 degrees C, V/sub CC/=5 V with a 30 pF load connected to the common I/O node.<<ETX>>

A 6-ns 256-kb BiCMOS TTL SRAM

The authors describe a 256-kb BiCMOS transistor-transistor logic (TTL)-compatible static RAM (SRAM) with typical address access time of 6 ns (5.0 V, 25 degrees C). The fast access time is due to the combination of new circuits and double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The high performance of the SRAM is due to the new BiCMOS circuit technologies. These include: (1) a low-input-capacitance BiCMOS gate, which reduced the gate loads in a decoder; (2) a reduced-load multiplexer-line sense amplifier; and (3) the two-level-presetting architecture of the TTL output buffer, which reduced the output-drive-current change rate to 20 mA/ns for a *8-b configured chip with a propagation delay time of 1.5 ns. The current change rate is about half that of the conventional-type output buffer. The fabricated SRAM is 4.25 mm*10 mm. >

3.3 V, novel circuit techniques for a 2.8-million-transistor BiCMOS RISC processor

3.3-V, high-speed circuit techniques, including a 0.6-ns single-ended common-base sense circuit, a 0.5-ns 22-b comparator circuit, and a 0.7-ns 3-input adder circuit, are applied to a 2.8-million-transistor RISC (reduced instruction set computer) microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS 3.3-V 4-metal-layer technology. The chip includes a 240-MFLOPS (million floating point operations per second) double-precision floating-point unit and a 24-kByte cache, and dissipates 17 W at 120 MHz.

A BiCMOS 32-bit execution unit for 70 MHz VLSI computer

A BiCMOS 32-bit execution has been developed to attain 70-MHz (typical) speed using 1.0-μm BiCMOS technology. The three important components are: (1) an arithmetic unit, which uses a 0.6-ns 8-bit carry propagation circuit; (2) a 2.5-ns 54-W×32-b four-port register file, which uses a BiCMOS sense circuit and dynamic bus drivers; and (3) a flag generator, which uses a novel all-bit-zero generation algorithm and generates in parallel with the arithmetic computation. A CLSI computer has been implemented with the above components, and 70-MHz register-register operation has been achieved

A 400MHz 160-word &#215; 64-bit 14-port floating-point register file macrocell for a superscalar RISC processor

A 400MHz 160-word × 64-bit 14-port floating-point register file for a superscalar RISC processor is presented. A large number of registers makes it possible to hide the long access latency of the main memory, and improves the performance of a processor by over double. A line boost circuit and a precharge circuit are successfully applied to the register file to realize 1.4ns read access. The register file makes use of 0.25µm CMOS technology with a 1.8V power supply. It has 856K transistors and dissipates 2.5W at 400MHz.