Yoji Nishio

A BiCMOS logic gate with positive feedback

It is noted that, as BiCMOS process technology is refined, the supply voltage must be reduced due to the lower endurance voltage of the devices and the larger power dissipation of the LSI chips. As the MOS drain current decreases with supply voltage, the base current from the MOS in a BiCMOS logic gate should then be sufficient for high-speed switching. Also, as the threshold voltage of the MOS becomes lower, a full logic swing function is necessary, even for BiCMOS gates, to ensure that a DC current does not flow in the next gate. These problems were solved with a BiCMOS logic gate with positive feedback, which was fabricated using a 0.5- mu m BiCMOS device and applied to a channelless gate array for a high-speed processor. Characteristics of the proposed logic gates are summarized. Experimental t/sub pd/ and P/sub d/ versus C/sub L/ characteristics for the three-input NAND at 4-V supply voltage are shown.<<ETX>>

A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM

This paper describes a 5-GByte/s data-transfer scheme suitable for synchronous DRAM memory. To achieve a higher data-transfer frequency, the properties were improved based on the frequency analysis of the memory system. Then, a bit-to-bit skew compensation technique that eliminates incongruent skew between the signals is described with a new, multioutput controlled delay circuit to accomplish bit-to-bit skew compensation by controlling transmission timing of every data bit. Simulated maximum data-transfer rate of the proposed memory system resulted in 5.1/5.8 GByte/s (321/365 MHz, /spl times/64 bit, double data rate) for data write/read operation, respectively.

5 GByte/s data transfer scheme with bit-to-bit skew control for synchronous DRAM

With the rapid increase of MPUs operating frequency, faster data transfer is required for memory systems. When the data bus frequency exceeds 100 MHz, controlling flight time variation becomes more crucial. This paper describes a 5 GByte/s data transfer scheme (313 MHz; /spl times/64 bit, double data rate) suitable for synchronous DRAM memory systems. A new multi-output controlled delay circuit of 30 ps resolution eliminates incongruent skew between data traces, and required improvements in the electrical characteristics are illustrated.

A feedback-type BiCMOS logic gate

The authors report on the development of a feedback-type BiCMOS logic gate using a 0.5- mu m BiCMOS technology. The propagation delay time of a three-input NAND gate with a 0.93-pF load is 245 and 290 ps at a supply voltage of 4.5 and 4 V, respectively. These values are about 1.4-1.2 times better than the 0.8- mu m BiCMOS gate operating at 5 V. A power dissipation of 0.4 mW was obtained with a 0.93-pF load, 4-V supply voltage, and 140-MHz operation. The power dissipation is comparable to that of a CMOS gate. >

A 200 ps 0.5 /spl mu/m CMOS gate array family with high speed modules

A 0.5 /spl mu/m CMOS gate array family with high speed modules is discussed. Measured access time of the 8 Kbit 2-port metallized RAM is 6.3 ns. Simulated access time of the 16 Kbit diffused RAM is 5.5 ns. Propagation delay time of the 2-input NAND is 200 ps at a standard load. Use of high performance internal logic circuits, high speed compiled RAM, improved GTL (Gunning Transceiver Logic), and PLL (Phase Locked Loop) realizes operation of over 100 MHz at 3.3 V. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment.<<ETX>>

Low-cost, Low-noise Vref Design for High-speed DDR Memory Modules

This paper discusses new Vref designs for high-speed memory modules. Our designs include chip resistors in series with Vref traces that reduce the total noise. We confirmed reduced noise of half the original through experiments

A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board Simulatig Actual Memory Module

Aiming to achieve double data rate-synchronous DRAM (DDR-SDRAM) at low-cost and with high noise tolerance by setting adequate Vref target impedance, we have established a measurement setup for Vref noise tolerance of DDR2-SDRAM on test board simulating actual memory module and measured various properties. The measured Vref noise tolerance has strong frequency-dependency; the higher the frequency, the larger the noise tolerance. We believe that this is because the intrinsic low pass filter consisted of on-chip electrical components in the test chip.

A 190 ps 0.5 mu m mixed BiCMOS/CMOS channelless gate array family

A mixed BiCMOS/CMOS channelless gate array family with three-metal-layer wiring using a 5 V version, 0.5 mu m BiCMOS technology is discussed. The speed and power performance of CMOS gates are superior to those of BiCMOS gates for light load capacitance. Therefore, by using CMOS and BiCMOS gates selectively according to the weight of the capacitance load, the performance of the BiCMOS gate array is enhanced. A novel mixed BiCMOS/CMOS basic cell structure which can be used as BiCMOS or CMOS gates was developed. The area efficiency of the developed basic cell is 16% better than that of the conventional basic cell. The wiring method of the power supply reinforcement lines of the third metal layer in a large chip was examined from the viewpoint of the number of useful basic cells. As a result, by locating the reinforcement lines at every basic cell, the number of useful basic cells is about 14% greater than that of another method in which the reinforcement lines are located at intervals of some basic cells. The propagation delay time of the two-input NAND is 190 ps at fanout 10 load. Under a light load, a pure CMOS NAND is faster, achieving 140 ps gate delay at fanout two load.<<ETX>>