Fumio Murai

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3- mu m electron-beam lithography. This memory cell has an area of 1.28 mu m/sup 2/. The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 mu m, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 mu m/sup 2/ because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta/sub 2/O/sub 5/ film equivalent to a 2.8-nm SiO/sub 2/ film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation. >

Transport characteristics of polycrystalline‐silicon wire influenced by single‐electron charging at room temperature

Conductance of ultrathin polycrystalline silicon wire was measured and periodic plateaus, which provide evidence of the Coulomb staircase at room temperature, are observed. This shows that single‐electron charging effects are important to transport in a semiconductor system at room temperature. The very small (∼10‐nm diam) silicon‐grain structure is presumably playing a key role in creating the observed effects. From the temperature dependence, the electron transport is clearly dominated by the thermal emission, whose activation energy is more than 400 meV. This reveals that the treatment beyond well‐established single‐electron tunneling, including thermal‐emission transfer, is essential to understand such high‐temperature charging effects in semiconductor systems.

Practical phase‐shifting mask technology for 0.3 μm large scale integrations

An i‐line phase‐shifting mask technology intended for practical use has been developed. The new technology can provide defect‐free phase‐shifting masks and can produce 0.3 μm large scale integration with large lithographic latitudes. The phase‐shifting masks manufactured here apply the following two major techniques. The first technique is to form phase‐shifting patterns on the chrome mask. This technique features single‐layer shifters using an organic spin on glass (SOG), a simple patterning process of the SOG, and a focused ion beam gas‐assisted etching repair process of shifter defects. The second technique is to create half‐micron chrome patterns using a high‐accuracy e‐beam writing system ‘‘EB‐MX’’ and high‐resolution chemically amplified e‐beam resist ‘‘PSR’’.

0.1- mu m gate-length superconducting FET

A superconducting field-effect transistors (FET) with a 0.1- mu m-length gate electrode was fabricated and tested at liquid-helium temperature. Two superconducting electrodes (source and drain) were formed on the same Si substrate surface with an oxide-insulated gate electrode by a self-aligned fabrication process. Superconducting current flowing through the semiconductor (Si) between the two superconducting electrodes (Nb) was controlled by a gate-bias voltage.<<ETX>>

GaAs dual-gate Schottky-barrier FET's for microwave frequencies

The benefits inherent in the tetrode structure and the potential of GaAs are combined to realized a dual-gate FET with low noise and a wide dynamic range at microwave frequencies. A design theory of the dual-gate FET is constructed on the basis of the Lehovec-Zuleeg model for single-gate FETs. The theory has led to a new device structure having a second gate with a deeper pinchoff voltage than the first which shows improved gain and noise performance. Also derived is the importance of minimizing parasitic feedthrough due, for example, to packages. Samples were fabricated using n-type epitaxial GaAs. The first and second gates were Schottky barriers, 1.2 and 2.5 µm long. The improved channel structure was accomplished by reducing the thickness of the epitaxial layer under the first gate. Samples were mounted and characterized in specially designed small-size ceramic packages with a feedthrough capacitance of only 0.004 pF. The possibility of gain control by means of second gate bias over a wide bandwidth is demonstrated.

Fast proximity effect correction method using a pattern area density map

This article proposes a new method for proximity effect correction that utilizes newly developed hardware. The correction algorithm modifies the exposure dose for each exposure point by referring to a pattern area density map. The only additional process in this method is virtual exposure to make the map. The virtual exposure is carried out once at the first use of the large‐scale integration circuit pattern and can be processed in only 30 s. The pattern area density map makes it possible to correct the proximity effect from the lower‐level patterns by the new map calculated from the two maps of lower level and exposing level. The usefulness of this method is verified by experiments using model patterns.

A 1.5 V circuit technology for 64 Mb DRAMs

A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future

Electron‐beam cell‐projection lithography system

An electron‐beam exposure system HL‐800D has been developed for the mass production of both quarter micron large‐scale integrated memories and application specific integrated circuits (ASICs). To achieve a productive level of throughput, the system utilizes a cell‐projection method combined with variable shaped method and a continuously moving stage at variable speed depending on the pattern density. The system is operated at a 50 kV acceleration voltage and a 1 μC/cm2 dosage. Three stage deflectors have been developed to assure high‐speed deflection and highly accurate positioning. A fast pattern controller generates patern data at 200 ns shot‐cycle‐time with the positioning error correction and proximity effect correction. A high‐speed ceramic XY stage and an automatic wafer loder have been developed. The system is operated by a workstation which also provides data conversion. The estimated throughput of the system is 11 wafers/h for 0.3 μm ASICs and 20 wafers/h for quarter micron memories.

Single-electron-memory integrated circuit for giga-to-tera bit storage

A single-electron-based integrated circuit is presented. An 8/spl times/8 b memory-cell array demonstrates read/write, ushering in a new phase of research on single-electron devices.

Process and device technologies for 1 Gbit dynamic random‐access memory cells

This article discusses the technological issues involved with continuing the miniaturization of dynamic random‐access memory cells into the gigabit era. Ever‐smaller giga‐generation dynamic random‐access memory cells require three‐dimensional high‐charge density capacitors with high‐e insulating films, leading to the need for further improvements in lithographic resolution for ever‐smaller, higher aspect ratio memory cells, and planarization technologies for reducing the memory‐cell height. This article demonstrates two technologies for meeting these two requirements: high acceleration energy electron‐beam lithography and KrF excimer‐laser phase‐shift photolithography, and plate‐wiring merge technology. Metal–insulator–metal 1.6 nm Ta2O5 CROWN capacitors and single Si3N4 spacer OSELO isolation technology for an experimental 1 Gbit dynamic random‐access memory chip are also discussed.