Hajime Hayakawa

Fabrication of Submicron Pattern with an EB Lithographic System Using a Field Emission (FE) Electron Gun

This paper describes the advantages of an EB Lithographic system using an FE electron gun and steered-beam vector scan to fabricate submicron patterns. Application of this system to submicron pattern writing is studied through exposure intensity distribution (EID) and exposure dosage for submicron patterns. The system can carry out submicron pattern writing with high resolution and small proximity effect. For example, the system provides submicron resist patters with line width larger than 0.5 µm and gap spacing 1.0 µm without proximity effect correction. The application of this system to VLSI submicron pattern writing is also demonstrated.

Investigation of the charging effect on thin SiO2 layers with the electron beam lithography system

The charging problem of a dielectric layer during direct exposure with an electron beam lithography system is investigated. Electron beam irradiation on a wafer with a dielectric layer such as SiO2 often causes charge buildup. This excessive accumulation of charge on the sample disturbs placement accuracy, and results in overlay errors. In order to analyze this charging problem, a metrology software package is used to measure the placement error of the exposed patterns on a target plane. Tested sample wafers are deposited with 0.2–1.5 μm SiO2, and then coated with 1 μm resist for exposure. To evaluate the charging dependence on electron beam current, a variable‐shaped electron beam lithography system which can easily change beam current is used. The results indicate that nongrounding 0.2 and 0.5 μm SiO2 do not show charge‐induced placement errors while 1 and 1.5 μm SiO2 show a definite placement error due to charging. On 1.5 μm Sio2 results indicate an electrostatic breakdown of SiO2, and no charging erro...

Charging effects on trilevel resist and metal layer in electron‐beam lithography

Charging effects of trilevel resist on a W layer have been investigated with an electron beam lithography system. The tungsten layer was deposited before the resist and the charge‐induced beam deflections were measured for several thick W layers. A test pattern was employed consisting of an array 21×21 cross marks in a 3 mm field. The charging effects show different dependencies on W thickness between 20 and 30 keV because of the W backscattering. To evaluate the correlation between the charging and the backscattering process in W and trilevel resist, reflected electron signals were detected from the developed resist marks. The resist mark signal has a double sloped inverse peak characteristic due to backscattering from the W layer and absorption by the resist mark. As a result, the charge‐induced beam deflections and the intensity of backscattered electrons are increased in proportion to W thickness. The authors will discuss the electron distribution caused by the electron beam and sample material intera...

Charging effects on trilevel resist with an e‐beam lithography system

The charging effect on a trilevel resist system was investigated with a variable‐shaped electron beam (e‐beam) lithography system. A test pattern which consists of two‐dimensionally arrayed marks was exposed on the trilevel resist and measured by the e‐beam. A method evaluating the correlation of repetitive measurement errors due to charging has been developed. This evaluation method was characterized such that the repetitive measurement and charging process occurred simultaneously without a conductive coating on the resist. The evaluation method of the charging process at 20 and 30 kV is demonstrated in this article. The resist result is different from that of silicon dioxide, and these phenomena are discussed together with the associated discharging processes.

Application of a high‐throughput electron‐beam system for 0.3 μm large scale integration

A high‐throughput electron‐beam direct writing technology has been developed. The new technology enables the manufacture of 0.3 μm large scale integration with a maximum throughput of 15 wafers/h, and the application of electron‐beam lithography for high‐volume large scale integrations. The throughput attained with this technology is 4–20 times higher than that of conventional technologies (e‐beam direct writing system: Hitachi HL‐700D; e‐beam resist: Hitachi RE‐5000P). This technology has been realized by utilizing a combination of the new e‐beam direct writing system HL‐800D and the new e‐beam resists RE‐4200N/PSR.

High-resolution and high-stability electromagnetic-deflection control system for EB lithography system

A stable high-resolution electromagnetic deflection control circuit for an electron-beam lithography (EBL) system has been developed. This deflection control circuit has enabled an EBL system to deal with a wide deflection area of 2.5-mm square having fine address units for a pattern placement of 1.25 nm. The deflection-control circuit consists of a new digital to analog converter (DAC) circuit, whose resolution is 21 bits, and a low-drift current-amplifier circuit. To achieve such high-stability and high-resolution, we had to develop a low noise-current cell structure for the new DAC circuit, because the output-signal noise of the DAC circuit is a major source of interference at the desired resolution. A local temperature control technique has been incorporated into the circuit to reduce fluctuations of the deflection control signal caused by ambient thermal variations. The low noise-current cell structure, which consists of multiple current buffers and low-pass filters, is placed between a constant current source circuit and a differential-switch circuit for each bit of the DAC circuit. The simulation results of the DAC circuit showed that the output-signal noise of the DAC circuit could be reduced to less than 0.4 nm rms, which is small enough to achieve the desired resolution. As the results of the experimentally evaluation of the deflection control circuit show, the total noise of the deflection-control signal obtained was less than 0.6 nm rms and the signal stability obtained was better than 0.3 nm rms. An evaluation of the performance of the new EBL system to which the new deflection control circuit was applied, showed that the critical-dimension accuracy obtained was better than 5 nm (3sigma) and the positioning accuracy obtained was better than 10 nm (3sigma) for the area controlled by electromagnetic deflector.

Electron-beam direct writing technology for fine gate patterning

Electron beam (EB) lithography along with photo lithography is a good candidate for fabricating fine patterns smaller than 200 nm. We examined the pattern fidelity which was one of the most important points for applying EB lithography for proto-typing ULSIs. We used a direct writing EB system with a shaped beam. In this paper, we applied EB direct writing for the gate fabrication of 250-nm CMOS devices. The fidelity in resist patterns was 55 nm. The deviation was 21 nm, and the variation was +/- 17 nm. We also applied EB/DW and i-line exposure for the gate fabrication of 350-nm CMOS devices, and measured the source-drain current in nMOS transistors. We compared the Lg fluctuations which were calculated by Ids fluctuations. The magnitude of the fluctuations around Lg- equals 350 nm with EB/DW was less than half of that with i-line. According to these result, EB lithography is very effective for fabricating very fine gates of ULSIs.

Highly accurate alignment technology for electron-beam lithography in mix-and-match with optical stepper

A novel alignment technology for electron-beam lithography is proposed for hybrid use with i-line steppers. This alignment technology was developed based on the evaluation of alignment characteristics and on the investigation of alignment errors in electron-beam lithography systems used in the mix-and-match process. In this alignment method, global alignment using representative chips on a wafer effectively achieves accurate overlay and high throughput. Overlay measurements showed that the deviation in the alignment error is smaller than 70 nm within 3 sigma.

High‐speed single‐layer‐resist process and energy‐dependent aspect ratios for 0.2‐μm electron‐beam lithography

For industrial application of an electron beam direct writing a single‐layer‐resist (SLR) process is more attractive than a multilayer‐resist process, because the SLR process is less expensive and provides a precise pattern transfer for 0.2‐μm large scale integration circuit fabrication. Three key factors for SLR process are (1) high acceleration voltage for clear latent image, (2) high‐contrast resist to attain a high‐aspect‐ratio pattern, and (3) rapid dissolving resist with little effect on the substrate. With 50‐kV acceleration voltage an aspect ratio of resist pattern of about 5 is obtainable using a chemically amplified resist. However, pattern collapse limits the maximum aspect ratio for smaller resist patterns. A positive‐tone resist (PSR) and negative‐tone resist (RE‐4200N) showed excellent characteristics for a SLR process with a 0.2‐μm feature size.