Fumito Imura

Analyses on Cleanroom-Free Performance and Transistor Manufacturing Cycle Time of Minimal Fab

In this paper, we introduce our developed clean-localized system for a cleanroom-free semiconductor manufacturing where a wafer is air-tightly transferred between the carrier and the machine via a load port and process in a clean chamber. The system has been applied to “minimal fab” specially designed to process a half-inch wafer for low-cost and low-volume device productions. To confirm the localized clean-performance of our system, we have measured the clean levels in process chamber of a machine and the wafer transfer system. Both are resulting in ISO class 4, while the clean level of the circumstance is in ISO class 9. In order to estimate the system performance in the issue of electronic device properties, we fabricate a traditional MOSFET using minimal fab for the entire process. The measured density of interface states (Dit) of the MOSFET was 7.7×1010 cm-2 and the off-leak current was 4×10-12 A. These are sufficiently low to confirm the acceptable particle contamination level of the system which has less impact on the device characteristics. Due to a compact size of the minimal machine, the wafer transfer distance between processes is minimized. The process efficiency of the minimal fab in terms of wafer transfer time and wafer waiting time is also studied.

COOL interconnect low power interconnection technology for scalable 3D LSI design

3D multi-chip stacking is a promising technology poised to help combat the “memory wall” and the “power wall” in future multi-core processors. However, as technology scales and the chip sizes increase due to the number of transistors, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. In this article, we introduce a TSV-based ultra-wide inter-chip connection technology that enables systems to have lower power consumption, higher scalability in its functionality and performance just by increasing the number/type of chips, allows to be manufactured with much more flexibility, and has a better cost/performance than conventional 2D SoC based designs.

Wide bus chip-to-chip interconnection technology using fine pitch bump joint array for 3D LSI chip stacking

We have developed a fabrication technology of fine-pitch cone shape Au bump array using nanoparticle deposition method for 3D LSI chip stacking. 1024-bit wide bus chip-to-chip interconnection circuit called Cool Interconnect has been also developed using fine-pitch bump joint array technology and precise flip chip bonding technology. Such a wide bus chip-to-chip interconnection is suitable instead of on-chip bus interconnection in multi-core architecture LSI system in order to achieve low power operation. We propose a testing approach to confirm the chip-to-chip interconnect electrical performance using scan path method and JTAG test method in 3D LSI chip stacking system. The preliminary data transmitting experiment of Cool Interconnect using designed, fabricated, and flip-chip stacked test LSI chips was successfully done under low power consumption with clock frequency of 50MHz.

Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large thermal gradients. It is crucial to understand the interaction between process parameters, such as wafer thickness, and the temperature profile in order to design high-performance 3DICs. In this paper we examine how the temperature profile of through-silicon via (TSV) bus driver/receiver cells are impacted by die thinning. While die thinning limits the ability for heat to diffuse into the wafer, it can also decrease the capacitance of the TSV which in turn decreases the drivers power, leading to an overall lower working temperature in some circumstances. In this work we have investigated the thermal effects of stacking 2-8 thinned ICs with TSVs, over a range of die thicknesses from 100 µ m to 25 µ m . Decreasing the die thickness from 100 µ m to 50 µ m provided the best balance with a 20% reduction in bus power at a cost of less than a 2% increase in driver temperature for all cases between 2 and 8 tiers. HighlightsDie thinning generally leads to higher system temperatures.TSV bus capacitances decrease when dies are thinned.Decreased TSV bus capacitances lead to lower power dissipation.Die thinning can be used to simultaneously decrease both power and temperature.

Development of micro bump joints fabrication process using cone shape Au bumps for 3D LSI chip stacking

3D LSI chip stacking technology have been developed using cone shape Au micro bumps fabricated by nanoparticle deposition method. The cone shape bumps with less than 10 um diameter are suitable for a thermocompression bump joint process with low temperature and low load force. High yield micro bump joints can be obtained. In this study, the property evaluation of the cone shape bumps, and the cone shape bump joints were investigated in details. The collapsed bump height and the electrical resistance can be controlled by compression force. The low resistance (average 8.6 mΩ) bump joint with a 10 μm diameter cone shape Au bump was successfully achieved.

Cool System scalable 3-D stacked heterogeneous Multi-Core / Multi-Chip architecture for ultra low-power digital TV applications

3-D Multi-Chip stacking is a promising technology to overcome the “memory wall”, “power wall”, “ILP wall”, and “utilization wall”. However, a chip to be stacked should be low-power enough to avoid heat issue. On the other hand, such system can benefit from its scalability, flexibility, short time-to-market, especially wide and short latency chip interconnect drives changes on microprocessor architecture. In this presentation, we introduce a scalable heterogeneous Multi-Core/Multi-Chip architecture that drastically reduced the operating clock frequency. Two chips will be shown that run at 50MHz for Digital TV applications, while the performance is comparable to 3GHz Core2Duo processor.

Investigation of effects of die thinning on central TSV bus driver thermal performance

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large thermal gradients. It is crucial to understand the interaction between process parameters, such as wafer thickness, and the temperature profile in order to design high-performance 3DICs. In this paper we examine how the temperature profile of a single TSV bus driver/receiver is impacted by die thinning. Die thinning limits the ability for heat to diffuse into the wafer, however decreasing the capacitance of the TSV can decrease the drivers power leading to an overall lower working temperature. In this work we found that thinning the top wafer with TSVs from 100 μm to 25 μm allowed for up to a 65% decrease in the steady-state temperature rise of a TSV driver/receiver running at 500 MHz.

Method for back-annotating per-transistor power values onto 3DIC layouts to enable detailed thermal analysis

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large spikes in individual device temperatures. These “hotspots” must be carefully analyzed at design time to ensure that the device temperatures will not cause the circuit to malfunction, and to assess the device temperatures impact on the longevity of the circuit. In this paper we present a tool flow for capturing accurate per-transistor power values in standard cell designs to allow for detailed thermal analysis. After extracting power values, High Definition Power Blurring is used to analyze the thermal performance of the inter-chip communication bus of a “Cool Interconnect” chip.

BGA packaging process for a device made by minimal fab

We have developed a novel packaging tool-set of 13 machines to support continuous manufacturing process from a half-inch wafer process line until ready to be used. The packaging tools are made under minimal fab standard so that a half-inch wafer can be attached on a metal-substrate without dicing. The method that we employed is a BGA (Ball Grid Array)-type solder array which consists of following processes; a compression molding, a laser via, a copper redistribution layer (RDL) patterning, a solder-ball mounting, and a reflow. The development of each machine process and the total packaging process integration has been carried out. In this paper, we introduce a BGA packaging result using only our newly developed tools.

Packaging in minimal fab: An integrated semiconductor line from wafer process to packaging process

The minimal fab concept using a half inch wafer was proposed in order to achieve a small semiconductor factory which is free from huge investment and is suitable to low-volume production. As a part of the minimal fab, we have developed a novel packaging-line which realizes a manufacturing system seamlessly integrating a wafer process-line with a packaging-line. The minimal packaging-line employs the same local clean technology and device transport system as the wafer process-line. Wafer level packaging of the minimal fab is designed for enveloping and protecting electronic devices fabricated on a half inch (φ12.5mm) wafer. This paper describes the packaging technologies and equipment in the minimal fab.