Michihiro Inoue

A fully parallel 10-bit A/D converter with video speed

Describes a 20 MHz conversion speed, fully parallel, analog-to-digital converter device which has been designed for use at video speed. Laser trimming technology has been adopted to improve nonlinearity errors brought about by reference voltage distortion to less than 1 mV to realize a /SUP 1///SUB 2/ LSB accuracy for the 10-bit A/D converter. The large number of comparator stages required by a parallel converter leads to a high number of components and large power dissipation. Therefore, a circuit with a reduced number of components and optimized power has been used. The process employed is a 3 /spl mu/m bipolar process, which integrates about 40000 elements onto a 9.2/spl times/9.8 mm chip.

A 4-Mbit DRAM with 16-bit concurrent ECC

A 256 K-word*16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8- mu m CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 mu m/sup 2/ with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC. >

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time. >

A new testing acceleration chip for low-cost memory tests

It is argued that the development of semiconductor memories has reached a turning point. In the multimegabit dynamic random access memories (DRAMs) of the future, major factors contributing to the chip cost are process complexity, die size, equipment cost, and test cost. If conventional test methods are used, test costs will grow at an especially rapid rate. A memory test concept called the testing acceleration chip, which could reduce future test costs a hundredfold and yet maintain AC testing reliability, is presented.<<ETX>>

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t/sub RAS/=50 ns (typical) at V/sub cc/=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V/sub SS/ shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4- mu m CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM. >

A monolithic 8-bit A/D converter with 120 MHz conversion rate

A monolithic 8-bit flash A/D converter is described which digitizes a 40-MHz signal at a conversion rate of over 100 MHz. To obtain full resolution and high accuracy at ultrahigh speed operation, a three-stage comparator with small talk back and other new logic circuits were designed. The process used is a self-aligned bipolar technology. Signal-to-noise ratio of 45 dB was measured at the 30-MHz input frequency.

A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers

A circuit design technique for suppressing asymmetrical characteristics in a high-density DRAM sense amplifier is discussed, and the effect of drain current imbalances between transistor pairs and the sensitivity of the sense amplifier are studied experimentally. A sense amplifier composed of parallel transistor pairs which have a reversed source and drain arrangement on a wafer is capable of suppressing the asymmetry effects to less than 15 mV in a range of submicrometer gate lengths and of reducing the layout area by about 43% compared with the conventional sense amplifier. >

Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of Ic= 10-9A. The typical distribution of the base-emitter offsets (ΔVBE) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of fTfor n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively.

New self-aligned complementary bipolar transistors using selective-oxidation mask

This paper describes a new self-aligned complementary transistor structure which makes a high-speed and high-accuracy analog bipolar LSI possible. This device structure consists of a 2 µm epitaxial layer, a non-LOCOS trench isolation burried with polycrystalline silicon, and complementary (NPN and vertical PNP) transistors which have self-aligned active base and emitter. The principal feature of the fabrication process is forming an active base and an emitter by ion implantations through the silicon nitride film using an oxidation film as a mask which lies upon an inactive base region. Because residual defects induced by the ion implantations are confined into the emitter region, the leakage current at the base-emitter junction is minimized. Current gains of the both transistors (NPN and PNP) are constant down to low current region IC=10-9A. The distribution of base-emitter offsets (ΔVBE) of transistor pairs is O.2mV as the standard deviation; 3σ. Maximum values of fTof NPN and PNP transistors are 6 GHz and 1.5 GHz, respectively.

Integrated circuit for an electronic musical instrument

The present invention is an integrated circuit for an electronic musical instrument comprising: a plurality of frequency divider chains receiving a plurality of input signals for dividing the frequencies of the input signals one after another and corresponding to a plurality of series of adjacent notes which are chromatically arranged in turn in a twelve-tone of a musical scale, respectively; keyer-gates for switching on and off the input signals and output signals of the frequency dividers of the frequency divider chains respectively; and adding means for adding at least two output signals of the keyer-gates which correspond to the adjacent notes chromatically arranged to each other, so as to produce output tone signals therefrom, respectively.