Samson Melamed

Design and CAD for 3D integrated circuits

High density through silicon vias (TSV) can be used to build 3DICs that enable unique applications in computing, signal processing and memory intensive systems. This paper presents several case studies that are uniquely enhanced through 3D implementation, including a 3D CAM, an FFT processor, and a SAR processor. The CAD flow used to implement for these designs is described. 3DIC requires higher fidelity thermal modeling than 2DIC design. The rationale for this requirement is established and a possible solution is presented.

Exploring compromises among timing, power and temperature in three-dimensional integrated circuits

Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing congestion, which also leads to longer interconnects. It is therefore very difficult to tell whether or not a particular system may benefit from 3D integration. In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology. Each design was partitioned and routed with varying numbers of tiers and thermal-via densities. A thermal-analysis methodology is developed to predict the final performance. Results show that the lowest energy per operation and delay are achieved with 4 or 5 tiers. These results show a reduction in energy and delay of up to 27% and 20% compared to a traditional 2DIC approach. In addition, it is shown that thermal-vias offer no performance benefit for the low-power system and only marginal benefit for the high-performance system

Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring

The degraded thermal path of 3-D integrated circuits (3DICs) makes thermal analysis at the chip-scale an essential part of the design process. Performing an appropriate thermal analysis on such circuits requires a model with junction-level fidelity; however, the computational burden imposed by such a model is tremendous. In this paper, we present enhancements to two thermal modeling techniques for integrated circuits to make them applicable to 3DICs. First, we present a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect. Second, we introduce a method for dividing the thermal response caused by a heat load into a high fidelity “near response” and a lower fidelity “far response” in order to implement Power Blurring high definition (HD), a hierarchical thermal simulation approach based on Power Blurring that incorporates the resistive mesh-based models and allows for junction-level accuracy at the full-chip scale. The Power Blurring HD technique yields approximately three orders of magnitude of improvement in memory usage and up to six orders of magnitude of improvement in runtime for a three-tier synthetic aperture radar circuit, as compared to using a full-chip junction-scale resistive mesh-based model. Finally, measurement results are presented showing that Power Blurring high definition (HD) accurately determines the shape of the thermal profile of the 3DIC surface after a correction factor is added to adjust for a discrepancy in the absolute temperature values.

Inter-die signaling in three dimensional integrated circuits

This work discusses a three dimensional network on chip (3D NoC) fabricated in the 0.18 mum MIT Lincoln Laboratories 3D FDSOI 1.5 V process. As a proof of concept, a three tier, 27 node, NoC test chip occupying 4 mm2 per tier was designed and tested. It is the first of its kind to demonstrate successful inter-tier signaling in a complex three dimensional design, and validates the technology as a viable alternative to the continued scaling of conventional CMOS processes. Simulated results show that when implemented in this 3D process, simple 3D mesh interconnection networks allow for the sharing of global routing resources for complex systems while consuming an extremely low 2 mW of power per transaction. Using these results, we establish the need for a 3D network simulator to quantify the advantage 3D circuit implementations have over 2D.

Junction-level thermal extraction and simulation of 3DICs

In 3DICs heat dissipating devices are stacked directly on top of each other leading to a higher heat density than in a comparable 2D chip. 3D integration also moves the majority of active devices further away from the heatsink. This results in a degraded thermal path which makes it more challenging to remove heat from the active devices. Gradient FireBolt was used to perform an appropriate 3D thermal analysis on a 1024-point, memory-on-logic 3DIC FFT processor for synthetic aperture radar (SAR). The chip was simulated with a spatial resolution of 80 nm, and was modeled to include the effect of each line of interconnect, as well as each via and fill structure exactly as drawn in the layout. Large isolated temperature spikes were found near groups of clock buffers at the edge of the SRAMs on the middle tier. It was found that lowering the simulation resolution and using composite thermal conductivities failed to accurately predict the location of these tentpoles.

Comparative analysis of two 3D integration implementations of a SAR processor

When designing 3DICs there are five major issues that differ from 2D that must receive special attention: power delivery, thermal density, design for test, clock tree design and floorplanning. Power delivery in 3D must receive special attention as 3D designs have larger supply currents flowing through the package power delivery pins, along with a longer power delivery path than in comparable 2D system. Thermal density is an issue as 3D integrated chips will have more heat density and less capacity to remove heat than a comparable 2D chip. 3D clock tree distribution is much more difficult than in 2D because the most commonly used methodologies and design tools are geared towards 2D designs and process variation between the different tiers makes it harder to keep skew, jitter and power consumption down. Design for test is harder in 3D because 3D vias provide another point of failure and post fabrication repairs such as Focused Ion Beam are more difficult to perform in 3D. Finally, floorplanning is drastically different in 3D than in 2D, and the four aforementioned issues must all be taken into account during 3D floorplanning. In this paper, all five design issues are explored in the context of a high-resolution memory-on-logic Synthetic Aperture Radar (SAR) processor. The SAR processor is chosen specifically as it requires a significant amount of memory bandwidth that is best met with the high I/O bandwidth afforded by a 3D process. The issues are examined in the context of two implementations for two different 3D integration processes. The first implementation was done in MIT Lincoln Laboratorys 3D FDSOI 1.5 V three tier process and is currently in fabrication. The second design is currently in the design stage, and will be fabricated in two tiers of Chartered Semiconductors 130 nm process 3D integrated with two tiers of high bandwidth DRAM using Tezzaron Semiconductors vertical interconnection technology.

A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits

A transient electrothermal simulation of a 3-D integrated circuit (3DIC) is reported that uses dynamic modeling of the thermal network and hierarchical electrothermal simulation. This is a practical alternative to full transistor electrothermal simulations that are computationally prohibitive. Simulations are compared to measurements for a token-generating asynchronous 3DIC clocking at a maximum frequency of 1 GHz. The electrical network is based on computationally efficient electrothermal macromodels of standard and custom cells. These are linked in a physically consistent manner with a detailed thermal network extracted from an OpenAccess layout file. Coupled with model-order reduction techniques, hierarchical dynamic electrothermal simulation of large 3DICs is shown to be tractable, yielding spatial and temporal selected transistor-level thermal profiles.

Pathfinder 3D: A flow for system-level design space exploration

Three dimensional integration technology has the potential to provide enhanced performance and device density gains beyond that available from technology scaling alone. However, it provides plethora of design choices for system designers. The full exploitation of the benefits of 3D integration requires a system-level exploration flow which can facilitate in finding an optimal 3D design by comparing possible early design choices. In this paper we present a flow for fast system-level exploration useful for path finding studies. The flow enables users to explore the tradeoff between different stacking and partitioning schemes in terms of performance, power, and temperature. We also present a free open source design kit compiler, FreePDK3D45 and a tool for fast floorplan evaluation of TSV-based digital architectures, Pathfinder3D. The open source design kit and architecture evaluator can help the community to research, learn and explore the various aspects of 3D integration. Using the proposed flow and design kit, we present a case study of 3D integration of a Network on Chip. This case study demonstrates system-level comparisons of the performance, power and temperature of different homogenously partitioned stacking schemes.

Compact Electrothermal Modeling of an X-band MMIC

Compact electrothermal modeling of lumped electrical devices and compact thermal modeling of volumetric materials enables efficient electrothermal modeling of microwave circuits. The compact thermal model of the body of an X-band MMIC is based on analytical solutions of the heat diffusion equation in thermal sub-volumes. The model is accurate and captures thermal nonlinearities. The model considers complex MMIC features such as surface metallization and vias, as well as the mounting configurations including lead-frame, carrier, and printed circuit board. This is coupled with electrothermal models of transistors and of resistors. The models are incorporated in a multi-physics simulator that uses the same model in both transient and harmonic analysis of an X-band LNA MMIC. Simulations are validated with steady-state thermal measurements

Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration

In this article we demonstrate a floating point FFT processor that leverages both 3D integration and a unique hypercube memory division scheme to reduce the power consumption of a 1024 point FFT down to 4.227μJ. The hypercube memory division scheme lowers the energy per memory access by 59.2% and increases the total required area by 16.8%. The use of 3D integration reduces the logic power by 5.2%. We describe the tool flow required to realize the 3D implementation and perform a thermal analysis of it.