G.A. Armstrong

A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors

Abstract Polysilicon thin film transistors (TFTs) differ from conventional silicon on insulator (SOI) transistors in that the TFT exhibits a fundamental gate length dependence of the voltage at which a kink occurs in the output characteristics. This difference is shown to be caused by the peak lateral electric field being strongly dependent on the doping density in an SOI transistor, but relatively insensitive to trap distribution in a TFT. Source barrier lowering which occurs in SOI transistors is absent in a TFT, where the increase in current is the result of a field redistribution along the channel. For very short gate lengths, the TFT exhibits a small pseudo-bipolar gain. Estimates of this bipolar gain can be made by simulation of TFT characteristics with and without impact ionisation. The magnitude of the gain is shown to be approximately inversely proportional to gate length.

Drain voltage limitations of MOS transistors

Abstract A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poissons equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poissons equation to an electrostatic one. The punch-through voltage VPT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, VBD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that VPT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. VBD, however, decreases as the channel length, oxide thickness and diffusion depth decrease. Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.

Strained-Si channel heterojunction p-MOSFETs

Abstract A simulation study of a short-channel strained-Si p-MOSFET is presented. An analytical model for hole mobility enhancement in strained silicon has been used in a two-dimensional (2D) device simulator to evaluate the strain dependence of the drain current and transconductance. Simulation results have been verified with experimental device results and the leverage of the strained-Si channel p-MOSFET over conventional Si p-MOSFETs is shown both at low temperature and room temperature. Optimal confinement of holes within the strained silicon occurs for a graded Si 0.7 Ge 0.3 buffer cap thickness of 40xa0nm. This layer structure gives rise to an enhancement in transconductance of up to 60%.

The distribution of mobile carriers in the pinch-off region of an insulated-gate field-effect transistor and its influence on device breakdown

Abstract A method of determining the distribution of injected carriers within the pinch-off region of an insulated-gate field-effect transistor is described. The analysis is based on two-dimensional solutions of both Poissons Equation and the current continuity equation for minority carriers, within a small region adjacent to the drain junction. The effect of carrier velocity saturation in the pinch-off region, on the carrier density distribution is assessed. Regions of maximum field are determined. The magnitude of the maximum field within the device is shown to be dependent on the concentration gradient of impurities at the edge of the drain diffusion.

Numerical simulation of transient emission from deep level traps in polysilicon thin film transistors

Numerical simulation has been used to model transient carrier emission from deep level traps in polycrystalline silicon (poly-Si) thin film transistors, and to validate the analytical approximations used to interpret DLTS measurements. The analytical analysis has been shown to yield substantially correct values for a typical double exponential poly-Si trap state density as a function of energy, to within +/-10%. The major source of discrepancy has been associated with the omission of the effects of displacement current from the analytical analysis.

Simulation of ultra thin film SOI transistors using a non-local ballistic model for impact ionisation

Abstract To model bipolar snapback in thin film SOI transistors accurately, it is necessary to employ a non-local model of impact ionisation. Such a model, based on the “Lucky electron” theory, has been incorporated in a two-dimensional device simulator. Accurate prediction of bipolar holding voltage has been obtained for SOI transistors with sub-micron gate lengths. The model has been applied to analyse separately the effects of both lightly doped source and lightly doped drain in maximising the holding voltage. The advantage of using ultra thin highly doped SOI films in conjunction with a lightly doped drain is discussed.

Investigation of Non‐classical Under lap Design on Linearity of a Folded Cascode Operational Transconductance Amplifier (OTA)

The significance of optimization of gate–source/drain extension region (also known as a non‐classical underlap design) in double gate (DG) silicon‐on‐insulator (SOI) FETs to improve the linearity performance of a low power folded cascode operational transconductance amplifier (OTA) is described. Based on a new figure‐of‐merit (FoM) involving AV, linearity, unity gain bandwidth fT and dc power consumption PDC, this article presents guideline for optimum design for underlap spacer s and film thickness Tsi to maximize the performance of OTA. It has been shown that FoM exhibited by an underlap DG MOSFET OTA gives significantly higher value (≅9) compared to a conventional single gate bulk MOSFET OTA. This is due to a combination of both higher fT, and higher gain AV for the same linearity at low power consumption of 360 μW. With gate length scaling, FoM continues to improve, primarily due to higher value of fT. A scaled bulk MOSFET OTA exhibits similar but much smaller enhancement in trend for FoM.

A model for the dependence of maximum oscillation frequency on collector to substrate capacitance in bipolar transistors

Abstract Parasitic effects associated with the collector degrade the frequency performance of a bipolar transistor. These effects include collector series resistance and collector-substrate capacitance. A simple analytical model has been derived to show the dependence of the maximum oscillation frequency fmax on these parameters. The significance of using bonded SOI material to reduce collector-substrate capacitance is discussed. The analytical model is used to predict the factor of improvement of this technology over conventional diffusion isolated bulk silicon technology. By considering the impact of process optimisation, an improvement in fmax by a factor of between two and three is predicted at maximum power output. By trading off this improvement in fmax for lower power operation, it is possible to achieve a significant reduction in power-delay product.