John R. A. Ayres

Influence of melt depth in laser crystallized poly-Si thin film transistors

The influence of film thickness and incident excimer laser energy density on the properties of poly-Si thin film transistors has been investigated and a coherent pattern of behavior has been identified which establishes controlled melt-through of the film as a key condition for achieving high quality devices. The conditions were correlated with the appearance of large grains and gave consistent results from both n- and p-channel devices, with carrier mobilities of more than 150 and 80 cm2/V s, respectively, and leakage currents of less than 2×10−14 A/μm. From a study of static irradiations, using a semi-Gaussian laser beam, the results are shown to be consistent with the super lateral grain growth (SLG) model. The trailing edge of the beam, when used in a swept mode, has been demonstrated to play an important role in extending the size of the energy window for this effect by re-setting the material into the SLG regime.

Deep levels of copper in silicon

Defect impurity levels have been examined in copper‐diffused p‐and n‐type silicon using deep level transient spectroscopy. Levels at Ev+0.09, Ev+0.23, and Ev+0.42 eV have been observed in both types of material, although the deeper levels were only oberved in n‐type material after post‐diffusion annealing at 200 °C. Associated with the appearance of these levels in n‐type material was another level at Ec−0.16 eV. This may be a further charge state of the center responsible for the Ev+0.23 eV and Ev+0.42 eV levels or the two centers may be decomposition products of a thermally unstable complex. Luminescence measurements have revealed the previously reported Cu‐Cu spectrum in all the copper‐diffused samples. The occurrence of this signal could not be correlated with the presence of the levels at Ev+0.23, Ev+0.42, or Ec−0.16 eV; this leaves the center at Ev+0.09 eV as the likely origin of the signal.

Laser crystallised poly-Si TFTs for AMLCDs

Abstract The technology for the fabrication of poly-Si TFTs on glass substrates has now reached a level of maturity such that the first commercial products are becoming available. The technology choice will be briefly reviewed and the reasons for the preferred use of excimer laser crystallisation will be summarised. Some of the key device and technology issues will be reviewed in this paper, including the role of the incident laser energy density in fabricating high performance TFTs and its dependence on film thickness. The issues discussed above have determined our design and fabrication of poly-Si AMLCDs and the results obtained from a 2-inch array, with full drive circuit integration, are illustrated.

Characterization of trapping states in polycrystalline‐silicon thin film transistors by deep level transient spectroscopy

Polycrystalline‐silicon (poly‐Si) thin film transistors (TFTs) have been assessed using deep level transient spectroscopy (DLTS) based on the measurement of current transients due to the thermal emission of carriers trapped at deep levels in the poly‐Si. Measurements were made on fully hydrogenated TFTs and the DLTS signal was found to vary continuously between 77 K and room temperature, without showing the characteristic peaks normally associated with point defects in single crystal Si. This demonstrates the existence of a continuous distribution of states through the band gap rather than discrete monoenergetic states. Analysis of the DLTS signal suggests the density of states increases rapidly toward the conduction band edge indicating the presence of a relatively high density of tail states. After annealing the TFTs at 450 °C the current DLTS signal was found to increase due to an increase in trap state density, which occurs because Si–H bonds are thermally unstable at this temperature. The increase in...

Defects and leakage currents in BF2‐implanted preamorphized silicon

High‐dose silicon implants have been used to preamorphize the surface of single‐crystal silicon prior to the implantation of low‐energy BF2. The preamorphization results in shallow junction formation with minimal channeling of the boron, but high concentrations of electrically active defects are formed, leading to excessive reverse bias leakage currents. Measurements of leakage current and deep‐level defects indicated that two distinct types of electrically active defects were important: those associated with what are probably complexes or clusters of point defects located near the far end of the range of the implanted silicon, and those associated with extended defects (loops) at the edge of the regrown amorphous region. The former defects were deep‐level donors present in high concentrations (>1017 cm−3) after regrowth of the amorphous layer at 600 or 700 °C and resulted in leakage currents >10−4 A/cm2. These centers could be annealed out at 800 °C reducing the leakage current to values between 5×10−8 a...

Characterisation of low temperature poly-Si thin film transistors

Abstract There is developing interest in using thin film transistors as active elements in a range of large area electronics applications. The characteristics of poly-Si thin film transistors (TFTs), processed at glass compatible temperatures, have been investigated. The particular features examined were the leakage current, hydrogenation mechanism and mobility. The hydrogenation was found to proceed by a lateral penetration through the gate oxide around the edges of the poly-Si gate finger. This led to a channel length dependence of sub-threshold slope in partially hydrogenated devices. In contrast, the leakage current, which was shown to be a generation current at the drain junction, did not require hydrogen penetration into the centre of the channel and hence passivation of the generation centres was channel length independent. The hydrogen diffusion coefficient in fine grain poly-Si was estimated at 350°C to be ∼1–10 × 10 −14 cm 2 / s depending upon the detailed material properties. Thermal crystallisation of LPCVD and PECVD amorphous silicon was found to be comparable with both leading to large dendritic grains and enhanced carrier mobility.

High-speed, short-channel polycrystalline silicon thin-film transistors

Results are presented on the performance of low-temperature, short-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs), with channel length down to 0.5 μm, and scaled gate oxide thickness down to 20 nm. Good TFT switching characteristics were obtained, and the uniformity of short-channel TFTs was shown to have a standard deviation of better then 10%, even for channel widths as small as 4 μm. The 0.5 μm TFTs have been incorporated into a 15-stage complementary pair metal-oxide-Si transistor ring oscillator, which, at a supply voltage of 3 V, operated with a delay/stage of ∼0.1 ns.

Control and analysis of leakage currents in poly‐Si thin‐film transistors

Control of leakage current in autoregistered columnar and a solid phase crystallized poly‐Si thin‐film transistors (TFTs) is discussed. For n‐channel TFTs, two parasitic leakage current paths, due to bulk conduction and back interface conduction, have been identified. It is demonstrated that these can be controlled by using sufficiently thin films and by low dose boron back channel implants, respectively. By these means, generation limited leakage currents, with values of <4×10−14 A/μm of channel width, have been obtained. The minimum leakage currents, for n‐ and p‐channel TFTs, display the well‐known field enhancement which we confirm can be described by phonon assisted tunneling. In well‐engineered TFTs, with subthreshold slopes of <1 V/dec, we show that the drain fields required to promote the tunneling process are independent of the trap state density and result entirely from two‐dimensional gate‐drain coupling effects. Therefore, improving the quality of the poly‐Si will not reduce the exponential de...

A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors

Abstract Polysilicon thin film transistors (TFTs) differ from conventional silicon on insulator (SOI) transistors in that the TFT exhibits a fundamental gate length dependence of the voltage at which a kink occurs in the output characteristics. This difference is shown to be caused by the peak lateral electric field being strongly dependent on the doping density in an SOI transistor, but relatively insensitive to trap distribution in a TFT. Source barrier lowering which occurs in SOI transistors is absent in a TFT, where the increase in current is the result of a field redistribution along the channel. For very short gate lengths, the TFT exhibits a small pseudo-bipolar gain. Estimates of this bipolar gain can be made by simulation of TFT characteristics with and without impact ionisation. The magnitude of the gain is shown to be approximately inversely proportional to gate length.

Differentiation of Effects due to Grain and Grain Boundary Traps in Laser Annealed Poly-Si Thin Film Transistors

A new physical model based on two dimensional simulations for high quality laser re-crystallised poly-Si thin film transistors is presented. It has been shown that to adequately explain the improved subthreshold slope and the lack of saturation of the output characteristics in these transistors, it is essential to distribute the density of defect states between traps in the grains alongside traps localised at grain boundaries. A double exponential density of states has been extracted for thin film transistors (TFTs) annealed at different excimer laser energies, using the field effect conductance method. By splitting the density of states between grain traps and grain boundary traps good fits to the output characteristics have been achieved. Lack of saturation is shown to be due to decrease in potential barrier at grain boundaries with increase in drain bias. At high gate voltages, however, evidence of a self-heating effect similar to that observed in silicon-on-insulator (SOI) transistors is apparent.