G. Anelli

Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects

We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELTs) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASICs designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELTs: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of ICs conceived with this design approach are finally drawn.

Noise characterization of a CMOS technology for the LHC experiments

Abstract After having reviewed the main noise sources in an MOS transistor the paper presents results about the noise performance of a 0.25 μm CMOS technology which is being extensively used to design radiation tolerant ASICs for the LHC experiments (the Large Hadron Collider at present under construction at CERN). The 1/ f and white noise are studied for n- and p-channel devices with five different gate lengths, in weak, moderate and strong inversion and for different drain to source and bulk to source biases. The noise degradation is measured after irradiation with 10 keV X-rays and after annealing. The results are commented in view of the use of these transistors in low-noise front-end circuits.

A new NMOS layout structure for radiation tolerance

A new transistor structure is presented to obtain radiation tolerance in commercial submicron CMOS technology without any process modifications. The NMOS transistor and field leakage normally induced by ionizing irradiation is remedied by acting on the work function of the transistor gate at the transistor edges. The technique also works in a CMOS process where transistor source and drains are silicided. Contrary to the enclosed layout transistor (ELT) previously proposed for this purpose, this new transistor structure does not limit the transistor width over transistor length (W/L) ratios to large values and thereby eliminates one of the most stringent constraints in the design of radiation tolerant circuits in standard CMOS. Measurements on fabricated devices demonstrate the functionality of the transistor structure and its radiation tolerance up to 40 Mrad(SiO/sub 2/).

Deep submicron CMOS technologies for the LHC experiments

Abstract The harsh radiation environment at the Large Hadron Collider (LHC) requires radiation hard ASICs. This paper presents how a high tolerance for total ionizing dose can be obtained in commercial deep submicron technologies by using enclosed NMOS devices and guard rings. The method is explained, demonstrated on transistor and circuit level, and design implications are discussed. A model for the effective W/L of an enclosed transistor is given, a radiation-tolerant standard cell library is presented, and single event effects are discussed.

VFAT2 : A front-end “system on chip” providing fast trigger information and digitized data storage for the charge sensitive readout of multi-channel silicon and gas particle detectors.

The architecture, key design parameters and results for a highly integrated front-end readout system fabricated as a single ASIC are presented. The chip (VFAT2) comprises complex analog and digital functions traditionally designed as separate components. VFAT2 contains very low noise 128 channel front-end amplification with programmable internal calibration, intelligent “fast OR” trigger building outputs, digital data tagging and storage, data formatting and data packet transmission with error protection. VFAT2 is designed to work in the demanding radiation environments posed by modern high energy physics experiments, in particular the Large Hadron Collider at CERN. Measured results are presented demonstrating full functionality and excellent analog performance despite intensive digital activity on the same piece of silicon.

First results from the ALICE silicon pixel detector prototype

Abstract System prototyping of the ALICE silicon pixel detector (SPD) is well underway. The ALICE SPD consists of two barrel layers with 9.83 million channels in total. These are read out by the ALICE1LHCb pixel chip, which has been developed in a commercial 0.25 μm process with radiation hardening by design layout. The readout chip contains 8192 pixel cells each with a fast analog preamplifier and shaper followed by a discriminator and digital delay lines. Test results show a pixel cell noise of about 110 electrons rms and a mean minimum threshold of about 1000 electrons rms before threshold fine tuning. Several readout chips have been flip-chip bonded to detectors using two different bump-bonding techniques (solder, indium). Results of radioactive source measurements of these assemblies are presented for 90 Sr and 55 Fe sources. Several chip-detector assemblies have been tested in a 150 GeV / c pion beam at CERN where an online efficiency of about 99% across a wide range of detector bias and threshold settings was observed. All preliminary investigations confirm the functionality of the chip and the chip-detector assemblies for the ALICE experiment.

An introduction to deep submicron CMOS for vertex applications

Abstract Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

A low-power 10 bit ADC in a 0.25 /spl mu/m CMOS: design considerations and test results

This paper presents the design and test of a low power analog to digital converter implemented in a commercial 0.25 /spl mu/m CMOS technology. The circuit has been developed to serve as a building block in multi-channel data acquisition systems for high energy physics (HEP) applications. Therefore medium resolution (10 bits), very low power consumption and high modularity are the key features of the design. In HEP experiments the resistance of the electronics to the ionizing radiation is often a primary issue. Hence the ADC has been laid-out using a radiation tolerant approach. The test results show that the chip operates as a full 10 bit converter up to a clock frequency of 30 MHz. No degradation in performance has been measured after a total dose of 10 Mrd (SiO/sub 2/).

3D Active Edge Silicon Detector Tests With 120 GeV Muons

3D detectors with electrodes penetrating through the silicon wafer and covering the edges were tested in the SPS beam line X5 at CERN in autumn 2003. Detector parameters including efficiency, signal-to-noise ratio, and edge sensitivity were measured using a silicon telescope as a reference system. The measured sensitive width and the known silicon width were equal within less than 10 mum.

The Alice silicon pixel detector

CERN European Organization for Nuclear Research, CH-1211 Geneva 23, Switzerland Universita degli Studi di Padova, I-35131, Padova, Italy Dipartimento IA di Fisica e Sez. INFN di Bari, I-70126,Bari,Italy Comenius University, SK-84215 Bratislava, Slovakia NIKHEF, National Institute for Nuclear Physics and High Energy Physics, 1098 SJ Amsterdam, The Netherlands Slovak Academy of Sciences, SK-04353, Kosice, Slovakia Universita di Roma I, La Sapienza, I-00185, Roma, Italy