G. Bruguier

Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations

A 3-D entire SRAM cell, based on a 0.35-/spl mu/m current CMOS technology, is simulated in this work with a DEVICE simulator. The transient current, resulting from a heavy ion strike in the most sensitive region of the cell, is studied as a function of the LET value, the cell layout and the ion penetration depth. A definition of the critical charge is proposed and two new methods are presented to compute this basic amount of charge only using SPICE simulations. Numerical applications are performed with two different generations of submicron CMOS technologies, including the determination of the sensitive thicknesses.

Single particle-induced latchup

This paper presents an up-to-date overview of the single-event latchup (SEL) hard failure mode encountered in electronic device applications involving heavy ion environment. This phenomenon is specific to CMOS technology. Single-event latchup is discussed after a short description of the effects induced by the interaction of a heavy ion with silicon. Understanding these effects is necessary to understand the different failures. This paper includes a description of the latchup phenomenon and the different triggering modes, reviews of models and hardening solutions, and finally presents new developments in simulation approaches.

SEU critical charge and sensitive area in a submicron CMOS technology

This work presents SEU phenomena in advanced SRAM memory cells. Using mixed-mode simulation, the effects of scaling on the notions of sensitive area and critical charge is shown. Specifically, we quantify the influence of parasitic bipolar action in cells fabricated in a submicron technology.

Evidence of the ion's impact position effect on SEB in N-channel power MOSFETs

Triggering of Single Event Burnout (SEB) in Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is studied by means of experiments and simulations based on real structures. Conditions for destructive and nondestructive events are investigated through current duration observations. The effect of the ions impact position is experimentally pointed out. Finally, further investigation with 2D MEDICI simulations show that the different regions of the MOSFET cell indeed exhibit different sensitivity with respect to burnout triggering. >

Simulation aided hardening of N-channel power MOSFETs to prevent single event burnout

2D MEDICI simulator is used to investigate hardening solutions to single-event burnout (SEE). SEE parametric dependencies such as carrier lifetime reduction, base enlargement, and emitter doping decrease have been verified and a p/sup +/ plug modification approach for SEE hardening of power MOSFETs is validated with simulations on actual device structures.

The latchup risk of CMOS-technology in space

The use of CMOS technology in space requires the careful evaluation of the latchup risk. The radiation tolerance of a standard 1.0 mu m high density technology and its hardened variants is studied. The internal currents and densities are read through dynamic two/three dimensional device simulations, performed on a complete description of the CMOS inverter cell and a simulated heavy ion strike. An evaluation of the capture cross section versus the ion energy is derived from the statistical distribution of ion tracks through the structure. >

The effect of layout modification on latchup triggering in CMOS by experimental and simulation approaches

The influence of certain geometrical parameters on latchup triggering in CMOS-1.2 /spl mu/m structure is studied by means of experiments and simulations on test structures. Electrical characterizations are made in order to validate quantitatively the analysis achieved by numerical simulations. The results of heavy ion irradiation from two different sources are given and discussed with regard to the influence of the same geometrical parameters on the sensitivity of the test structures to latchup. >

Cell design modifications to harden an N-channel power IGBT against single event latchup

A device simulator is used to analyze the heavy ion induced failure mechanism in insulated gate bipolar transistors (IGBTs) and to investigate hardening solutions. Single event latchup was already identified as the failure mechanism. Lateral and vertical modifications of the P/sup +/ plug are proposed to reduce the efficiency of the parasitic thyristor, responsible for the latchup, and validated by 2D-simulations on a N-channel IGBT cell structure.

A new method for determining the transient photocurrent in an irradiated diode

An analytical expression of the photocurrent in a n-p junction exposed to an ionizing radiation pulse is derived by using a specific decomposition of the minority carrier density. Modeling can be applied to any shape of actual radiation pulses, in particular with significant rise times. Comparisons with experiments and numerical resolutions have shown the validity of the modeling.<<ETX>>

Simulation of heavy ion latchup cross section curves

The latchup sensitivity of 1 /spl mu/m CMOS structures when subjected to heavy ion irradiation is studied. Cross section curves and threshold LETs obtained by 2D and 3D device simulations are compared to the experimental results.