G. Cocciolo

A fast and low noise charge sensitive preamplifier in 90 nm CMOS technology

A fast charge sensitive preamplifier was designed and built in a 90 nm CMOS technology. The work is part of the R&D effort towards the read out of pixel or small strip sensors in next generation HEP experiments. The preamplifier features outstanding noise performance given its wide bandwidth, with a ENC (equivalent noise charge) of about 350 electrons RMS with a detector of 1 pF capacitance. With proper filtering, the ENC drops to less than 200 electrons RMS. Power consumption is 5 mW for one channel, and the closed loop bandwith is about 180 MHz, for a risetime down to 2 ns in the fastest operation mode. Thanks to some freedom left to the user in setting the open loop gain, detectors with larger source capacitance can be read out without significant loss in bandwidth, being the rise time still 5.5 ns for a 5.6 pF detector. The output can drive a 50 ? terminated transmission line.

Low Power Analog Design in Scaled Technologies

In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some drawbacks are introduced in term of power leakage and reliability. Moreover, the scaled technology lower supply voltage requirement has led analog designers to find new circuital solution to guarantee the required performance.

A 6.9mA 5 bits 90nm 1GS/s ADC without calibration for UWB application

Power consumption of high-speed low-resolution ADCs can be reduced by means of calibration. However, this solution presents some drawbacks like allocating a calibration time, calibration algorithm complexity, calibration circuit implementation, etc. In alternative, this paper presents a 5-bit 1Gs/s ADC without calibration, realized in a 90nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparators, operating with a fixed bias current. These comparators present a reduced kickback noise, allowing increasing the input transistors sizes in order to improve the matching. The ADC current consumption is equal to 6.9mA from a 1.2V supply.

A 54dB-DR 1-GHz-bandwidth continuous-time low-pass filter with in-band noise reduction

In this paper a 5th order low-pass continuous time analog filter in CMOS 45nm technology is presented. The filter design is based on a single compact cell used to synthesize five poles. The circuit performs the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 1-GHz -3dB-bandwidth is obtained by a prototype of the filter simulated in 45nm CMOS technology node (also Process-Voltage-Temperature simulations are available). The overall power consumption is 9mW from a single 1.2V supply voltage. 54dB@THD>40dBc is the SNR at 0dB gain.

A CMOS low-power SoC for HID and LED lamps ballast

In this work a new concept of hybrid lamps burner is presented. The High Intensity Discharge (HID) lamps and the new generation Light Emitting Diodes (LED) lamps can be driven by the same electronic ballast using this hybrid ASIC in 0.35µm CMOS technology. In the state-of-art the electronic ballasts are managed by powerful general-purpose devices (usually FPGA or microcontroller). These devices are not customized for the specific application. Thus they have a larger area occupation and power consumption compared to ASIC solution. The designed ASIC power consumption is 35 mW and the package area is about 6.5 cm2 against 550 mW and 6.5 cm2 for commonly used PIC 18FXX2.

A programmable active-RC complex filter for wireless communications

A programmable active-RC complex filter synthesized from Tow-Thomas Low-Pass prototype is proposed in this paper. The filter features tunable Intermediate Frequency (fIF), and can be programmed by the external. In addition a tunable damping structure allows to guarantee a minimum image rejection for any value of the tunable range. The filter is implemented in a 0.18µm CMOS technology, consumes 0.36mW and its response ranges from 40kHz to 100kHz (5kHz per step), the minimum image rejection is 62dB. The maximum in-band integrated output noise is 132µVrms, while an in-band IM3 of 20dBc is obtained with vin=140mVrms.

A 4 th order CMOS 65nm wideband low power analog filter for wireless receivers

A 4th-order continuous-time band-pass filter for wireless receivers is here presented. The filter is composed by the cascade of two active RC cells. The overall pass-band (32dB) gain is distributed for each cell in order to minimize the power consumption. The operating point issues due to the low VDD/VTH ratio - a value of 2 is typical in CMOS 65nm technologies and down - have been solved by adding a proper bias circuit to the filter. The f@-3dB deviation due to the technological spread, aging and temperature in active RC circuits is adjusted by using variable capacitor with 4 bits of resolution. The device in 65nm CMOS technology consumes 1.3mW from a single 1.2V supply voltage, features −10dBm-IIP3 and 1.6mVrms output integrated noise over the pass-band − 300kHz÷8MHz.

A 115µW UWB Programmable Gain Amplifier for intelligent tire personal area network

In this paper the complete design of a Programmable Gain Amplifier embedded in UWB receiver is presented. The receiver is part of a System-On-Chip placed inside the car tire (with the aim to interchange data with the car control unit) where dynamic stress, temperature and aging are very important issues, resulting in severe design constraints for CMOS analog integrated circuits. Furthermore, the SoC is biased by vibration-based energy scavenger, and a as consequence, very low power is available for the integrated circuits. High input impedance is required from system level constraints and this is achieved with MOS input devices, exploiting dual differential input Opamp. The PGA gain is programmable in the 15dB-to-50dB range with 1dB step. For the maximum gain level (50dB), the Input-Referred-Noise power spectral density is lower than 20nV/vHz. From a single 1V supply, for the minimum gain level (15dB), a 0.8Vzero-peak output signal is processed with THD=−40dBc.

A 1.3mW CMOS 65nm 4 th order 52dB-DR continuous-time analog filter for DVB-T receivers

In this paper a 8.2MHz-f@−3dB bandwidth Filter-&-Amplifier to be embedded in a DVB-T RX chain is presented. The filter has been integrated in 65nm CMOS node, working with a VDD/VTH ratio (supply/threshold voltage) as low as 2. Operating point issues due to low VDD/VTH ratio has been resolved by a proper bias circuit. Since such bias circuit is part of the filter circuit, its impact on filter performance have been studied and considered in the design. Power consumption is minimized by using a novel algorithm based on Matlab procedure, which guarantees the minimum power consumption for a given transfer function, noise and linearity requirements. The device consumes 1.3mW from a single 1.2V supply voltage, features −10dBm-IIP3 at 32dB pass-band Gain, and 1.6mVrms output integrated noise over the pass-band (300kHz÷8.2MHz).

A 1V 115μW 20nV/√Hz 15–50dB-range PGA with 5MHz bandwidth for UWB personal area network

In this paper a 115μW Programmable Gain Amplifier (PGA) in 90nm CMOS technology is presented. The PGA is embedded in the baseband chain of a low-data-rate UWB PAN receiver. Since a vibration-based energy scavenger powers the receiver, low power consumption is required, while maintaining large dynamic range and wide-band frequency response. Moreover, high input impedance is required from system level constraints and this is achieved with MOS input devices, exploiting dual differential input Opamp. The PGA gain is programmable in the 15dB-to-50dB range with 1dB step. For the maximum gain level (50dB), the Input-Referred-Noise power spectral density is lower than 20nV/√Hz. From a single 1V supply, for the minimum gain level (15dB), a 0.8Vzero-peak output signal is processed with THD=−40dBc.