S. D'Amico

A 4th-order active-G/sub m/-RC reconfigurable (UMTS/WLAN) filter

A fourth-order low-pass continuous-time filter for a UMTS/WLAN receiver of a reconfigurable terminal is presented. The filter uses the cascade of two Active-Gm-RC biquad cells. A single opamp is used for each biquad and its unity-gain-bandwidth is comparable to the filter cut-off frequency. Thus, the opamp power consumption is strongly reduced w.r.t. other closed-loop filter configurations. The cut-off frequency deviation due to the technological spread, aging and temperature variation is adjusted by an on-chip tuning circuit. The device in a 0.13 mum CMOS technology occupies a 0.9 mm2 area and it consumes 3.4 mW and 11 4.2 mW for the UMTS and WLAN, respectively. The full chip has been designed using an automatic design tool, which is validated by the agreement between the experimental results and the expected performance

Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/performance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-mum CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 muVrms and 163 muVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1-5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mum CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two active- Gm-RC biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The - 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The -3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 mum CMOS technology with VTHN ap 0.25 V and VTHP ap 0.3 V, the filter operates with a supply voltage as low as 0.55 V. The filter (total area=0.47 mm2) consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18/spl mu/m CMOS

A 3-to-5GHz quadrature analog correlation RX for UWB impulse radio draws 16mA at 20Mpulses/s, making it suitable for low-power low-data-rate applications. The RX is fully integrated in a CMOS 0.18mum process and comprises an LNA, quadrature LO generation and mixers, baseband filtering, an integrator, timing circuitry, and an ADC

A 6 th -Order 100μA 280MHz Source-Follower-Based Single-loop Continuous-Time Filter

The source follower is a well known basic building block for CMOS design. A capacitively loaded source follower acts as a 1st-order low- pass filter and exhibits excellent linearity, especially with reduced overdrive voltages. In these source-follower features have been used advantageously in the design of a 2nd-order (biquadratic) low-pass filter and a 4th- order filter, which was made by cascading two 2nd-order cells. We have used this technique to design single-loop high-order source- follower-based continuous-time filters that, like ladder filters, have transfer functions that are insensitive to component variations. An efficient CMOS realization demonstrates the principle an achieves lower power and smaller area than other solutions.

1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters

Two versions of a baseband block composed by a 8-bit current-steering DAC and a fourth-order low-pass reconstruction filter are realized in a 0.13-mum CMOS technology to be embedded in multistandard wireless transmitters. In order to satisfy the specifications of WLAN IEEE 802.11a/b/g, UMTS, and Bluetooth standards, the proposed devices can be digitally programmed, adjusting the DAC conversion frequency and the low-pass filter cut-off frequency. For the WLAN case, the DAC operating frequency and the filter bandwidth are set to 100 MHz and 11 MHz, respectively, for the UMTS case, they are equal to 50 MHz and 2.5 MHz, and for the Bluetooth case, they are equal to 50 MHz and 1 MHz. The first device is reconfigurable between WLAN and UMTS, and the second one between WLAN and Bluetooth. The two fabricated devices operate from a single 1.2-V supply voltage and occupy a 0.8 mm 2 and 0.7 mm2 die area, respectively. The power consumption is optimized according to the operation mode and is 8 mW in WLAN mode, 8.4 mW in UMTS mode, and 5.4 mW in Bluetooth mode. For all the considered standards, the measured OIP3 is larger than 28 dBm, while the SFDR is 54 dB for WLAN, 61 dB for UMTS, and 63 dB for Bluetooth

A 255 MHz Programmable Gain Amplifier and Low-Pass Filter for Ultra Low Power Impulse-Radio UWB Receivers

A 90 nm-CMOS power-optimized analog baseband chain for ultra-low-power impulse-radio ultra-wideband (IR-UWB) receivers is presented. The proposed device merges the functions of a programmable gain amplifier (PGA) and a low-pass filter (LPF). It consists of the cascade of three biquadratic cells made up by opamps in a series-shunt configuration, which features high input impedance, low load effects in the cascade blocks, and better frequency response. The opamp parameters are included in the overall biquad transfer function. This allows getting very low power performance, since the opamp bandwidth is not required to be much larger than the filter cutoff frequency. Moreover, the current consumption is optimized according to the selected gain level (1.3 mA at 0 dB-gain up to 1.9 mA at 40 dB-gain). The PGA features a 0-40 dB programmable gain range with a 5 dB gain-step. The LPF performs a sixth-order 255 MHz low-pass frequency response. For the overall chain the IIP3 is 14 dBm at 0 dB gain, while the input referred noise is 12.5 nV/√Hz at 40 dB gain.

A high-band IR-UWB chipset for real-time duty-cycled communication and localization systems

A 90nm, IR UWB, duty-cycled transceiver chipset, for operation from 7 to 9.8GHz and compliant to the IEEE802.15.4a and the upcoming IEEE802.15.6 standard, is presented. The complete, duty-cycled transmitter provides +1dBm peak output power, consuming 4.4mW. The receiver front-end shows −88dBm sensitivity at 0.85Mbps and a digital synchronization algorithm enables real-time duty cycling, resulting in a mean power consumption of 3mW.

UWB Radio Transceivers For Ultra Low Power and Low Data Rate Communications

Radio transceivers relying on impulsed radio UWB signals show a strong potential for low data rate communications at an ultra low power consumption. They are for instance proposed by the IEEE 802.15.4a low-rate wireless personal area networks standard (LR-WPAN) to support low data rates, low power and low complexity short-range radio communications. In this paper, we give an overview of our recent UWB radio front-end designs along with new system simulation results, and derive specifications for a 15.4a receiver. The system simulations are used to balance the partitioning of gain, noise and distortion for next generation transceivers and allow to analyze the expected communication range of IEEE 802.15.4a systems in various channel conditions. The free-space wireless channel loss as well as 9 propagation scenarios are taken into account.