G. de Haan

True-motion estimation with 3-D recursive search block matching

A new recursive block-matching motion estimation algorithm with only eight candidate vectors per block is presented. A fast convergence and a high accuracy, also in the vicinity of discontinuities in the velocity plane, was realized with such new techniques as bidirectional convergence and convergence accelerators. A new search strategy, asynchronous cyclic search, which allows a highly efficient implementation, is presented. A new block erosion postprocessing proposal further effectively eliminates block structures from the generated vector field. Measured with criteria relevant for the field rate conversion application, the new motion estimator is shown to have a superior performance over alternative algorithms, while its complexity is significantly less. >

Robust motion-compensated video upconversion

The quality of field-rate conversion improves significantly with motion-compensation techniques. It becomes possible to interpolate new fields at their correct temporal position. This results in smooth motion portrayal without loss of temporal resolution. However, motion vectors are not always valid for every pixel or object in an image. Therefore, visible artifacts occur wherever such wrong vectors are used on the image. One effective method to solve this problem is the use of non-linear filtering. In this method, a wrongly interpolated pixel is either substituted or averaged with neighbouring pixels. We introduce and evaluate a new and very robust upconversion algorithm which is based on the non-linear filtering approach. It is unique in that it estimates motion vector reliability and uses this information to control the filtering process. This algorithm outperforms others in its class, especially when we have complex image sequences.

De-interlacing of video data

A new de-interlacing algorithm is proposed, suitable for high-quality flicker-free display of television images, for matrix type of displays, and as a basis for scan-rate conversions. The algorithm applies motion estimation and compensation techniques to achieve a high performance for moving and stationary image parts. This paper provides details of the new algorithm and an evaluation showing the relative performance of the proposal and a set of newly proposed and/or commercially available methods.

IC for motion compensated de-interlacing, noise reduction, and picture rate conversion

An IC for consumer television applies motion estimation and compensation for high-quality video format conversion. It achieves a perfect motion portrayal for all source material and many display formats.

Real-time 2-3 Pull-down Elimination Applying Motion Estimation/compensation In A Programmable Device

A software package realizes real-time video processing on a commercially available programmable device. The software implements a motion estimator and a picture rate convertor to provide judder-free display of movie material broadcast in 2-3 pull-clown mode. A new object-based true-motion estimation algorithm efficiently uses the VLIW core of the processor. It permits quasi-simultaneous motion estimation/segmentation for a fixed maximum number of objects.

An evolutionary architecture for motion-compensated 100 Hz television

In this paper, recently developed algorithms for high quality motion-compensated up-conversion are combined in a new architecture closely resembling that of current 100 Hz consumer television sets. By merging the motion estimation and the motion compensation part, the estimated silicon area could be reduced to a level where the entire functionality can be realized with one processing chip replacing the currently used 100 Hz processing chip. This enables a simple evolution towards motion compensated 100 Hz TV, considered to be very attractive. The architectural choice, and the wish to share expensive memories, requires some modifications in the motion estimator and up-convertor design which are discussed. The specific case of movie programs is dealt with, and it is also shown how the evolutionary architecture can achieve a significantly improved motion portrayal for this movie material. >

Application specific instruction-set processor template for motion estimation in video applications

The gap between application specific integrated circuits (ASICs) and general-purpose programmable processors in terms of performance, power, cost and flexibility is well known. Application specific instruction-set processors (ASIPs) bridge this gap. In this work, we demonstrate the key benefits of ASIPs for several video applications. One of the most compute- and memory-intensive functions in video processing is motion estimation (ME). The focus of this work is on the design of a ME template, which is useful for several video applications like video encoding, obstacle detection, picturerate up-conversion, 2-D-to-3-D video conversion, etc. An instruction-set suitable for performing a variety of ME functions is developed. The ASIP is based on a very long instruction word (VLIW) processor template and meets low-power and low-cost requirements still providing the flexibility needed for the application domain. The ME ASIP design consumes 27 mW and takes an area of 1.1 mm/sup 2/ in 0.13 /spl mu/m technology performing picturerate up-conversion, for standard definition (CCIR601) resolution at 50 frames per second.

IC for motion-compensated 100 Hz TV with smooth-motion movie-mode

An IC for consumer 100 Hz television is presented. It applies motion estimation and compensation techniques for very high-quality field rate up-conversion and a judder-free motion portrayal of movie material. The IC is fabricated with an 0.8 /spl mu/m CMOS process.

De-interlacing of video data using motion vectors and edge information

EDDI (edge dependent de-interlacing) is a new method for effectively removing jagged edges from interlaced video. It detects and quantifies edges for optimal image interpolation, with applications in high-end as well as in economy de-interlacing.

A video signal processor for motion-compensated field-rate upconversion in consumer television

In todays 100 Hz television sets, the display rate is doubled by displaying incoming fields twice. Moving objects are displayed at an incorrect position in the interpolated fields. In the new generation 100 Hz television sets, this artifact is solved by motion-compensated interpolation. Known algorithms for motion estimation and compensation require a huge number of computations. A 3D-recursive block matching algorithm makes possible a one-chip solution. The presented IC is also capable of jitter-free motion portrayal of movie material (25 Hz to 60 Hz upconversion), noise reduction, and vertical zoom.