G. P. Carver

Specific contact resistivity of metal-semiconductor contacts-a new, accurate method linked to spreading resistance

A method to determine the specific contact resistivity of metal-semiconductor contacts has been developed. It allows the separation of the total series resistance between two contacts into the contributing component resistances. The principle of the method is the subtraction of the semiconductor spreading resistance from the total two-contact resistance. This requires geometrically well-defined small contacts that are fabricated precisely by lithographic methods. Using this method, accurate values were obtained for the specific contract resistivity of an aluminium-1.5% silicon alloy to p-type silicon wafers having dopant densities from 5*10/sup 14/ to 2*10/sup 20/ cm/sup -3/. The specific contact resistivity values are lower than previously published values obtained using earlier methods in which parasitic and nonideal effects could not be quantified or eliminated. The lower values indicate that contact resistance has a less-limiting effect on the performance of integrated circuits than presently believed. >

An X-ray monochromator crystal which detects the bragg condition

Abstract We have fabricated a (111) silicon X-ray monochromator crystal with a diode diffused into its surface. Without suffering any apparent degradation in its or rocking-curve width at the Bragg condition, the crystal provides a dc current which changes dramatically at the diffraction of a monochromatic X-ray beam. The current change is directly attributable to extinction at the Bragg angle. It provides a new means to align the two crystals of a double-crystal X-ray monochromator using a feedback circuit.

High spatial resolution mapping of resistivity variations in semiconductors

Abstract A new approach to the mapping of resistivity variations in semiconductors uses probe sites provided by an array of lithographically defined contacts with a density of 60,000 sites cm −2 . One- or two-probe spreading resistance or four-point-probe resistance measurements can be made. Solutions of the Laplace equation and measurements on Si that had been ion-implanted to form abrupt boundaries in resistivity are used to show that the spatial resolution of the technique is determined primarily by the spacing of the measurement sites, not by the spreading of the current from the contacts. The technique has been implemented with resolution of lateral variations in resistivity of 45 μm in extent and ±5% in magnitude from the background resistivity. As an example application, a study of the resistivity variations of a Si boule with pronounced growth striations is presented.

High-mobility CMOS transistors fabricated on very thin SOS films

It is reported that the mobility of CMOS transistors fabricated on very thin silicon-on-sapphire (SOS) films is a function of the film growth rate. Transistors with mobilities nearly as high as those obtained on 1.0- mu m-thick films have been fabricated on SOS films 0.2 mu m thick that have been grown at growth rates above 4 mu m/min. >

Growth and properties of high-quality very-thin SOS films

The increased emphasis on submicron geometry CMOS/SOS devices has created a need for high quality silicon-on-sapphire films with thicknesses of the order of 0.1 to 0.2 µm. To date the only viable way of producing high quality SOS films with these thicknesses has been through the application of recrystallization and regrowth techniques. The need for as-grown, high-quality, very-thin SOS films has prompted a study of film quality vs growth rate for films with thicknesses in the 0.1 to 0.2 µm range as a possible way of producing thin high-quality SOS films. It has been found that film quality increased as the growth rate increased. It was possible to produce films as thin as 0.1 µm with mobilities nearly as high as 1 µm films, if the film growth rate was higher than 4 µm/ min.

Silicon Quality Versus Thickness For Novel Silicon On Boron Phosphide Soi Process

Results are reported for a single temperature Si-BP-Si process which utilizes 0.2 and 0.4 μm of high resistivity BP covered by a single 1–5 μm silicon epitaxial layer on which PMOS devices were fabricated. Transistor and capacitor measurements were used to characterize the quality of the silicon films. Impurity concentrations on 1.0 and 2.0 μm silicon layers were as high as 3×10 17 cm −3 due to auto doping from the BP layer. MOS transistors manufactured on these layers did not work properly. Device characteristics improved on thicker silicon layers. The impurity concentration was as low as 10 15 cm −3 on the 5.0 μm silicon layers. Surface state densities were found to be as low as 5×10 11 eV −1 cm −2 with subthreshold currents as low as 10 −11 amperes. On all wafers the subthreshold slope varied from 90 to 100 mV/decith little variation due to silicon thickness. Linear and saturation mobilities were process limited with values on the 5.0 μm layers as high as 250 and 160 cm 2 /V-s respectively. Characteristics of devices fabricated on 5 μm silicon layers were comparable to those of devices fabricated on bulk silicon processed at the same time indicating high quality silicon growth.