Joseph J. Kopanski

Scanning capacitance microscopy measurements and modeling: Progress towards dopant profiling of silicon

A scanning capacitance microscope (SCM) has been implemented by interfacing a commercial contact‐mode atomic force microscope with a high‐sensitivity capacitance sensor. The SCM has promise as a next‐generation dopant‐profiling technique because the measurement is inherently two dimensional, has a potential spatial resolution limited by tip diameter of at least 20 nm, and requires no current carrying metal–semiconductor contact. Differential capacitance images have been made with the SCM of a variety of bulk‐doped samples and in the vicinity of pn junctions and homojunctions. Also, a computer code has been written that can numerically solve Poisson’s equation for a model SCM geometry by using the method of collocation of Gaussian points. Measured data and model output for similar structures are presented. How data and model output can be combined to achieve an experimental determination of dopant profile is discussed.

Characterization of two‐dimensional dopant profiles: Status and review

The National Technology Roadmap for Semiconductors calls for development of two‐ and three‐dimensional dopant profiling methods for calibration of technology computer‐aided design process simulators. We have previously reviewed 2D dopant profiling methods. In this article, we briefly review methods used to characterize etched transistor cross sections by expanding our previous discussion of scanned probe microscopy methods. We also mention the need to participate in our ongoing comparison of analysis results for test structures that we have provided the community.

Two‐dimensional scanning capacitance microscopy measurements of cross‐sectioned very large scale integration test structures

Scanning probe technology, with its inherent two‐dimensionality, offers unique capabilities for the measurement of electrical properties on a nanoscale. We have developed a setup which uses scanning capacitancemicroscopy (SCM) to obtain electrical information of cross‐sectioned samples while simultaneously acquiring conventional topographical atomic force microscopy(AFM) data. In an extension of our work on very large scale integration cross sections, we have now obtained one‐dimensional and two‐dimensional SCM data of cross sections of blanket‐implanted, annealed Si wafers as well as special test structures on Si. We find excellent agreement of total implant depth obtained from SCM signals of these cross‐sectioned samples with conventional secondary ion mass spectrometry(SIMS) profiles of the same samples. Although no modeling for a direct correlation between signal output and absolute concentration has yet been attempted, we have inferred quantitative dopant concentrations from correlation to SIMS depth profiles obtained on the same sample. By these means of indirect modeling, we have found that our SCM technique is sensitive to carrier density concentrations varying over several orders of magnitude, i.e., <1×1015 to 1×1020 atoms/cm3, with a lateral resolution of 20–150 nm, depending on tip and dopant level.

Calibrated nanoscale dopant profiling using a scanning microwave microscope

The scanning microwave microscope is used for calibrated capacitance spectroscopy and spatially resolved dopant profiling measurements. It consists of an atomic force microscope combined with a vector network analyzer operating between 1–20 GHz. On silicon semiconductor calibration samples with doping concentrations ranging from 1015 to 1020 atoms/cm3, calibrated capacitance-voltage curves as well as derivative dC/dV curves were acquired. The change of the capacitance and the dC/dV signal is directly related to the dopant concentration allowing for quantitative dopant profiling. The method was tested on various samples with known dopant concentration and the resolution of dopant profiling determined to 20% while the absolute accuracy is within an order of magnitude. Using a modeling approach the dopant profiling calibration curves were analyzed with respect to varying tip diameter and oxide thickness allowing for improvements of the calibration accuracy. Bipolar samples were investigated and nano-scale de...

Boron‐implanted 6H‐SiC diodes

Ion implanted planar p‐n junctions are important for silicon carbide discrete devices and integrated circuits. Conversion to p‐type of n‐type 6H‐SiC was observed for the first time using boron implantation. Diodes were fabricated with boron implants at 25 and 1000 °C, followed by 1300 °C post‐implant annealing in a furnace. The best diodes measured at 21 °C exhibited an ideality factor of 1.77, reverse bias leakage of 10−10 A/cm2 at −10 V, and a record high (for a SiC‐implanted diode) breakdown voltage of −650 V.

Silicon nanowire on oxide/nitride/oxide for memory application

We report the fabrication and characterization of Si nanowire memory devices with oxide/nitride/oxide stacked layers as the gate dielectrics and charge storage media. The devices were fabricated by using photolithography to pattern the metal contacts to the Si nanowires grown on pre-defined locations. A large memory window with high on/off-state current ratio due to the small radius and intrinsic doping of the Si nanowire is obtained. In addition, the simple reversible write/read/erase operations have been implemented with these memory devices. The dynamics of the nanowire/nitride charge exchange and its effect on the threshold voltage and memory retention have been investigated.

Precise Alignment of Single Nanowires and Fabrication of Nanoelectromechanical Switch and Other Test Structures

The integration of nanowires and nanotubes into electrical test structures to investigate their nanoelectronic transport properties is a significant challenge. Here, we present a single nanowire manipulation system to precisely maneuver and align individual nanowires. We show that a single nanowire can be picked up and transferred to a predefined location by electrostatic force. Compatible fabrication processes have been developed to simultaneously pattern multiple aligned nanowires by using one level of photolithography. In addition, we have fabricated and characterized representative devices and test structures including nanoelectromechanical switches with large on/off current ratios, bottom-gated silicon nanowire field-effect transistors, and both transfer-length-method and Kelvin test structures

Scanning capacitance microscopy measurement of two-dimensional dopant profiles across junctions

Cross-sectioned p+/p and p–n junction test structures were imaged with a scanning capacitance microscope (SCM). To maintain a constant difference capacitance, our SCM utilizes an electronic attenuator circuit with a dynamic range of 20 V to less than 1 mV. Dopant profiles are extracted from SCM images using a formalism, which rapidly determines the theoretical SCM response from a database of calculated C–V curves. A dopant profile from a p+/p junction determined via constant difference capacitance SCM is compared to a secondary ion mass spectroscopy profile from similar structures.

Influence of Metal–MoS2 Interface on MoS2 Transistor Performance: Comparison of Ag and Ti Contacts

In this work, we compare the electrical characteristics of MoS2 field-effect transistors (FETs) with Ag source/drain contacts with those with Ti and demonstrate that the metal-MoS2 interface is crucial to the device performance. MoS2 FETs with Ag contacts show more than 60 times higher ON-state current than those with Ti contacts. In order to better understand the mechanism of the better performance with Ag contacts, 5 nm Au/5 nm Ag (contact layer) or 5 nm Au/5 nm Ti film was deposited onto MoS2 monolayers and few layers, and the topography of metal films was characterized using scanning electron microscopy and atomic force microscopy. The surface morphology shows that, while there exist pinholes in Au/Ti film on MoS2, Au/Ag forms a smoother and denser film. Raman spectroscopy was carried out to investigate the metal-MoS2 interface. The Raman spectra from MoS2 covered with Au/Ag or Au/Ti film reveal that Ag or Ti is in direct contact with MoS2. Our findings show that the smoother and denser Au/Ag contacts lead to higher carrier transport efficiency.

Carrier concentration dependence of the scanning capacitance microscopy signal in the vicinity of p–n junctions

Scanning capacitance microscopy (SCM) was used to image (1) boron dopant gradients in p-type silicon and (2) identical boron dopant gradients in n-type silicon. The bias voltage dependence of the apparent p–n junction location in the (SCM) images was measured. The theoretical bias voltage dependence of the apparent p–n junction location of the same structures was determined using a two-dimensional, numerical Poisson equation solver. The simulations confirm that, for symmetric step p–n junctions, the apparent junction coincides with the electrical junction when the bias voltage is midway between the voltage that produces the peak SCM response on the p-type side and the voltage that produces the peak response on the n-type side. This rule is only approximately true for asymmetrically doped junctions. We also specify the extent of the region on the junction high and low sides from which valid carrier profiles may be extracted with a simple model.