G. Ph. Alexiou

Target Localization Utilizing the Success Rate in Infrared Pattern Recognition

The architecture of an indoor target localization system employing a small number of infrared-emitting diodes and sensors is presented in this paper. The properties of infrared light and magnetic fields have already been exploited for position localization in distances of several centimeters. Ultrasonic waves and laser light can be used for longer distance estimation if the system is capable of accurately measuring the time of flight of the reflected signals. The proposed approach intends to cover a distance of several meters without requiring high accuracy measurements and sensors of increased precision. The digital infrared patterns that are transmitted from a constant position are recognized by a pair of sensors mounted on the moving target, with varying success rate depending on the distance and the angular displacement from the transmitter. Processing the success rate instead of the analogue signal intensity requires low-cost digital microcontroller systems of moderate precision and computational power. Moreover, longer distances can be covered since attenuated, noisy, or scrambled patterns are also important for the position estimation in the proposed approach. A proper modeling of the pattern recognition success rate is presented in order to estimate distances of several meters with an adjustable estimation error. The use of multiple infrared pattern transmitting devices results in extension of the area covered and a reduction of the estimation error due to additional crosschecks that may be accomplished. The area covered can be increased by a factor between 20% and 100% depending on the allowed range overlapping of the transmitting devices. The potential topology of these devices is also discussed and analyzed. The presented system can be used in several virtual reality and robotics applications

Design, simulation and performance evaluation of a single-electron 2-4 decoder

In this paper, we present a single-electron 2-4 decoder built using single-electron devices. The circuit is designed using a proper tool based on a Monte Carlo technique. First a single-electron AND gate is studied and then the 2-D decoder circuit is designed and studied. The results proved that the circuit was a 2-4 decoder, while the behaviour of the free energy of the system (which was calculated to be 4.90x10^-^1eV) and the stability diagram verified the correct functioning of the circuit.

Low power dissipation in BIST schemes for modified Booth multipliers

Aiming at low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for modified Booth multipliers. Reduction of the power dissipation is achieved by: (a) introducing a suitable test pattern generator (TPG) built of a 4-bit binary and a 4-bit Gray counter, (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. The achieved reduction of the total power dissipation is from 44.1% to 54.9%, the average reduction per test vector is from 21.4% to 36.5% while the reduction of the peaks is from 15.8% to 34.3%, depending on the implementation of the basic cells and the size of the MBM. The test application time is also reduced by 28.9% while the introduced BIST scheme implementation overhead is very small.

A core generator for arithmetic cores and testing structures with a network interface

We present Eudoxus, a tool for generation of architectural variants for arithmetic soft cores and testing structures targeting a wide variety of functions, operand sizes and architectures. Eudoxus produces structural and synthesizable VHDL and/or Verilog descriptions for: (a) several arithmetic operations including addition, subtraction, multiplication, division, squaring, square rooting and shifting, and (b) several testing structures that can be used as test pattern generators and test response compactors. Interaction with the user is made through a network interface. Since the end user is presented with a variety of unencrypted structural cores, each one describing an architecture with its own area, delay and power characteristics, he can choose the one that best fits his specific needs which he can further optimize or customize. Therefore, designs utilizing these cores arc completed in less time and with less effort.

Low Power Single Electron Or/Nor Gate Operating at 10GHz

The design and simulation of a single-electron OR/NOR gate is being presented using a Monte Carlo based tool. Both the OR/NOR behavior and the stability were verified while the free energy behavior of the circuit was also examined. The results confirmed that the circuit behaved as an OR/NOR gate, depicting improved characteristics than previously published single electron OR circuits, achieving a really fast operational speed at low power. Moreover, the noise through the circuit was nearly diminished, while a stable behavior of the circuit was verified without any noise present at the output points.

A complementary single-electron 4-bit multiplexer

The design and simulation of a single-electron 4-1 complementary multiplexer is being presented using two Monte Carlo based tools. Both the behavior and the stability of the circuit were verified while its free energy and its speed were also examined and analyzed. The results confirmed that the circuit behaved as a complementary multiplexer. Moreover, the currents through the circuit were examined under the operating temperature, while a stable operation of the circuit was verified without any noise present at the output points.

EUDOXUS: a WWW-based generator of reusable arithmetic cores

Presents a WWW-based tool for the generation of arithmetic soft cores for a wide variety of functions, operand sizes and architectures. The tool produces structural and synthesizable VHDL and/or Verilog descriptions and covers several arithmetic operations, such as addition, subtraction, multiplication, division, squaring, square rooting and shifting. Therefore, designs requiring arithmetic cores, as for example those in digital signal processing and multimedia applications, can be completed faster and with less effort.

Design and simulation of an embedded DRAM cell made up of MOSFETs having alternative gate dielectrics

Design and construction of new sub-micron MOSFETs with alternative gate dielectrics has emerged as a new technology for use in high-performance logic or low power memory circuits. The modelling of the new devices needs to take into account the effects that the new dielectrics have on the MOS device performance. In this paper, we examine such effects in terms of both capacitance and leakage current effects. First, we investigate the role of the parasitic capacitances appearing at the MOS device due to either material related processes or metallization. These capacitances are modelled accordingly in order to derive the device characteristics. Then, leakage currents are taken into account and the whole device is simulated using a 90 nm technology based on the BSIM4 model equations, suitably modified to account for these effects. The application of such devices on memory circuits is examined in order to take into account device parameters such as the threshold voltage, ouput currents and timing. As a result, the design of an embedded DRAM based on the MOSFETs with the alternative gate dielectrics is presented and analysed. The single MOSFET behaviour and subsequently the DRAM circuit performance are presented and the relevant characteristics are derived. As a result, the simulation revealed low output currents for the MOSFETs and high refresh rates for the DRAM circuits. Deviations from the ideal case are examined and solutions and further work are proposed.

Defect related effects on the reliability and performance of an embedded DRAM cell designed with MOSFETs with alternative gate dielectrics

The design of an embedded DRAM based on MOSFETs with alternative gate dielectrics is presented and analysed. Design and evaluation of NMOS devices with high-k dielectric gate insulators and DRAM circuits took place. Reliability parameters of the NMOS devices constructed with (Ba,Sr)TiO3 gate dielectrics were examined. A 90 nm technology model and the BSIM4 Spice equations were used in order to derive the device behaviour and the DRAM circuit performance. The simulation revealed low output currents for the MOSFETs and higher decay times for the DRAM circuits constructed using the devices with the alternative gate dielectrics.

A methodology for the implementation of MOSFETs with a high-k dielectric gate material on the design of 90 nm technology circuits

Up to date, MOSFETs have been made through well established techniques that use SiO2 as the gate dielectric and the related design issues are well established. The need to scale down device dimensions allowed researchers to seek for alternative materials, in order to replace SiO2 as the gate dielectric. The implementation of such MOS devices in memory or logic circuits needs to take into account the effects that the use of the new gate dielectrics has on parameters such as the threshold voltage and the drain current. Hence, parameters such as the high dielectric constant values, extra oxide charges and process related defects at the physical level must be taken into account during the device design. As far as circuit applications are concerned, these changes may substantially affect the required performance. This paper presents and provides proposals about the issue of replacing commonly used parameters of the MOSFET modelling with new parameters, in which the presence of a gate dielectric with different properties from those of SiO2 is taken into account. A stepwise procedure is described for the new device design. Moreover, a case study is presented which examines a memory circuit built up by such new technology devices. In particular, this paper presents and analyses the design of a DRAM cell made up of MOSFETs with an alternative gate dielectric. The 90 nm technology and the BSIM4 model equations are used to derive the single MOSFET behaviour and subsequently the DRAM circuit performance. The results are analysed and compared to those obtained from conventional SiO2 devices. A cell layout is provided and the DRAM circuit characteristics are also presented.