Maciej Bellos

Scan cell ordering for low power BIST

Power dissipation during scan-based testing has gained significant importance in the past few years. In this work we examine the use of transition frequency based on scan cell ordering techniques in pseudorandom scan based BIST in order to reduce average power dissipation. We also propose the resetting of the input register of the circuit together with ordering of its elements to further reduce average power dissipation. Experimental results indicate that the proposed techniques can reduce average power dissipation up to 57.7%.

Test Set Embedding Based on Phase Shifters

In this paper we present a new method for designing test pattern generators (TPG) for the embedding of precomputed test sets. The proposed TPG is based on the use of an LFSR and phase shifters and produces the exact test set. The proposed TPG compares favorably, with respect to test application time and/or hardware overhead, to the already known approaches.

An efficient test vector ordering method for low power testing

This paper presents a novel test vector ordering method for average power consumption minimization. The proposed method orders the test vectors taking into account the expected switching activity at the primary inputs and at a very small set of internal lines of the circuit under test. The computational time required by the proposed method is very small while the power reduction achieved is very close to the best, with respect to power reduction, most time-consuming method. Experimental results show that apart from average power reduction, the proposed method achieves significant peak power reduction too.

A core generator for arithmetic cores and testing structures with a network interface

We present Eudoxus, a tool for generation of architectural variants for arithmetic soft cores and testing structures targeting a wide variety of functions, operand sizes and architectures. Eudoxus produces structural and synthesizable VHDL and/or Verilog descriptions for: (a) several arithmetic operations including addition, subtraction, multiplication, division, squaring, square rooting and shifting, and (b) several testing structures that can be used as test pattern generators and test response compactors. Interaction with the user is made through a network interface. Since the end user is presented with a variety of unencrypted structural cores, each one describing an architecture with its own area, delay and power characteristics, he can choose the one that best fits his specific needs which he can further optimize or customize. Therefore, designs utilizing these cores arc completed in less time and with less effort.

Low power testing by test vector ordering with vector repetition

Test vector ordering with vector repetition has been presented as a method to reduce the average as well as the peak power dissipation of a circuit during testing. Based on this method, in this paper we present some techniques that can be used to further reduce the average power dissipation. Experimental results validate that the proposed techniques achieve considerable savings in energy and average power dissipation while reducing the length of the resulting test sequences compared to the original method.

Deterministic BIST for RNS adders

Modulo 2/sup n/ -1 adders as fast as n-bit 2s complement adders have been recently proposed in the open literature. This makes a residue number system (RNS) adder with channels based on the moduli 2/sup n/, 2/sup n/ - 1, and any other of the form 2/sup k/ - 1, with k < n, faster than RNS adders based on other moduli. We formally derive a parametric, with respect to the adder size, test set, for parallel testing of the channels of an RNS adder based on moduli of the form 2/sup n/, 2/sup n/ - 1, 2/sup k/ - 1, 2/sup l/ - 1, ..., with l < k < n. The derived test set is reusable; it can be used for any value of n, k, l, ..., regardless of the implementation library used and is composed of n/sup 2/ + 2 test vectors. A test-per-clock BIST scheme is also proposed that applies the derived test vectors within n/sup 2/ + 2n cycles. Static CMOS implementations reveal that the proposed BIST offers 100 percent postcompaction fault coverage and an attractive combination of test time and implementation area compared to ROM and FSM-based deterministic BIST or LFSR-based pseudorandom BIST.

Low power test set embedding based on phase shifters

A new efficient method for test set embedding based on phase shifters was recently proposed This method suffers from high average and peak power consumption. In this work we propose a new phase shifter-based test set embedding method, which, by using interleaving and two LFSRs that change state in a non-overlapping way, significantly reduces the average and peak power consumption.

Path delay fault testing of Benes multistage interconnection networks

In this paper we present two methods for path delay fault testing of circuit-switched Benes Multistage Interconnection Networks (MINs) with centralized control. Although the number of paths is O(n/sup 3/), the first method exploiting the inherent parallelism of the Benes MIN requires O(n/sup 2/) pairs of test vectors. In the second method we propose the selection of a minimal subset of paths, that are robustly testable by only O(log/sub 2/n) test vector pairs. The delay along all other paths can be calculated based on the selected path delays.

Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks

In this paper we consider path delay fault testing of a class of isomorphic Multistage Interconnection Networks (MINs) with centralized control using as representative the nxn Omega network. We show that the number of paths is 3n2-2n and we give a method for testing those applying only 2(3n-2) pairs of test vectors. We also show that this is the least number of test vector pairs that are required for testing all paths of the MIN. We also give a path selection method such that: a) the number of selected paths, that is, the number of paths that must be tested, is a small percentage of all paths and the propagation delay along every other path can be calculated from the propagation delays along the selected paths, b) all the selected paths are tested by using 2(3log2n+1) test vector pairs. Both methods derive strong delay--verification test sets.

Deterministic test vector compression / decompression using an embedded processor

Test data compression and on-chip decompression using an embedded processor has already been proposed for test data volume and test time reduction as well as for use of slower testers without decreasing test quality. On the other hand, scan cell reordering methods have been proposed to overcome the problem of high average power dissipation during scan based external testing. In this paper we propose a scan cell ordering based test vector compression method, which reduces test data volume up to 87.3%. The decompression of the test data is based on the use of an embedded processor.