G.S. Kar

Effect of carbon on lattice strain and hole mobility in Si1-xGex alloys

AbstractPseudomorphic Si1-xGex and partially strain compensated

Series resistance and mobility degradation factor in C-incorporated SiGe heterostructure p-type metal–oxide semiconductor field-effect transistors

{\text{Si}}_{1 - x - y} {\text{Ge}}_x {\text{C}}_y

Hall mobilities in B-doped strained Si1−xGex and Si1−x−yGexCy layers grown by ultrahigh vacuum chemical vapor deposition

layers with different Ge and C fractions have been grown at 500 °C by ultra high vacuum chemical vapor deposition on Si (100) substrates. The degree of strain compensation of the layers has been investigated by high resolution X-ray diffraction and simple application of the linear elasticity theory. The surface morphology of the layers has been characterized by atomic force microscopy. The dependence of Si–Si Raman mode vibrations on strain and composition of binary and ternary alloys have been explained with experimental and theoretically calculated results. The Hall hole mobility is found to increase with decreasing compressive strain or effective Ge content in the layer throughout the temperature range of 120–300 K.

Temperature-dependent electrical properties of plasma-grown gate oxides on tensile-strained Si0.993 C0.007 layers

The potential of ZrO2 thin film as a high-K gate dielectric for scaled MOSFET devices has been studied. ZrO2 has been deposited directly on a Si0.8Ge0.2 substrate by reactive RF magnetron sputtering. An equivalent oxide thickness of < 20 Å with a leakage current of the order of 10-4 A/cm2 at 1 V has been obtained. Well-behaved capacitance-voltage characteristics with an interface state density of 2 × 1011 cm-2eV-1 have been achieved. The deposited dielectric exhibits low charge trapping under constant current stressing.

Characteristics of UHVCVD grown Si/Si1-x-yGexCy/Si quantum well heterostructure

We have fabricated p-type metal–oxide semiconductor field-effect transistor (p-MOSFET) devices with channel lengths from 0.8–10 μm on strained Si/Si0.8Ge0.2/Si and partially strain compensated Si/Si0.793Ge0.2C0.007/Si heterolayers. The device characteristics, the source–drain resistance and the mobility degradation factor have been studied for control-Si, Si0.8Ge0.2 and Si0.793Ge0.2C0.007 devices over the temperature range of 300–77 K. Though a significant improvement in the drive current of Si0.793Ge0.2C0.007 devices has been observed compared to the control-Si and Si0.8Ge0.2 devices at room temperature, the performance of ternary devices at 77 K has been found to be inferior to that of binary devices. This has been found to be due to the higher source–drain resistance and mobility degradation factor of Si0.793Ge0.2C0.007 MOSFET devices at cryogenic temperature.

Ultrathin oxynitride films grown on Si0.74Ge0.26/Si heterolayers using low energy plasma source nitrogen implantation

Abstract Fabricated strained Si/Si0.8Ge0.2/Si heterojunction PMOSFET devices have been used to calculate the hole mobility in surface-Si and buried-SiGe channels. A simple analysis based on the inversion layer mobility model has been used to find the current contribution of the buried-SiGe channel to the total drain current. The ‘true’ effective mobility enhancement in the buried channel of the fabricated Si0.8Ge0.2 PMOSFET device has thus been extracted over a temperature range of 77–300 K. The validity of the model has been verified by calculating the drain current as a function of drain voltage at different values of gate bias considering the estimated effective mobility of both parasitic-Si and buried-SiGe channels.

Effective mobility and alloy scattering in the strain compensated SiGeC inversion layer

Hall mobilities in a temperature range of 80–300 K have been measured in fully strained Si1−xGex and partially strain-compensated p-type Si1−x−yGexCy alloy layers grown on Si (100) by ultrahigh vacuum chemical vapor deposition. The effect of the addition of C on strain compensation of Si1−xGex films has been studied by high-resolution x-ray diffraction analysis. The Hall hole mobility is found to increase with decreasing compensative strain or effective Ge content in the layer throughout the studied temperature range. The effect of a Si-cap layer on the hole mobility of Si1−x−yGexCy film has been investigated.

Hole velocity overshoot in partially strain compensated Si0.793Ge0.2C0.007 inversion layers

Ultra-thin (<10 nm) gate oxides have been grown directly on tensile-strained Si0.993 C0.007 layers at a low temperature using microwave O2-plasma. The changes in gate voltage (ΔVg), flat-band voltage (VFB), oxide charge density (Qox/q) an interface state density (Dit) have been studied using a metal-oxide-semiconductor structure over the temperature range of 77–450 K. Inversion capacitance increases with temperature above 400 K, leading to a transition from high-frequency to low-frequency characteristics. The dominant types of charges in the oxide are found to be strongly temperature dependent. It is found that charge-trapping properties under Fowler–Nordheim (F–N) constant-current stressing are significantly improved with increasing temperature.