S. Maikap

Low-Power Switching of Nonvolatile Resistive Memory Using Hafnium Oxide

Nonstoichiometric hafnium oxide (HfOx) resistive-switching memory devices with low-power operation have been demonstrated. Polycrystalline HfOx (O:Hf=1.5:1) films with a thickness of 20 nm are grown on a titanium nitride (TiN) bottom electrode by commercial atomic layer deposition. Platinum (Pt) as a top electrode is used in the memory device. Voltage-induced resistance switching is repeatedly observed in the Pt/HfOx/TiN/Si memory device with resistance ratio is greater than 10. During the switching cycles, the power consumptions for high- and low-resistance states are found to be 0.25 and 0.15 mW, respectively. At 85 °C, the memory device shows stable resistance switching and superior data retention with resistance ratio is greater than 100. In addition, our memory device shows little area dependence of resistance-switching behavior. The anodic electrode containing noble metal Pt serves an important role in maintaining stable resistance switching. The resistance switching in the HfOx films is thought to be due to the defects that are generated by the applied bias. The nonstoichiometric HfOx films are responsible for the low SET and RESET currents during switching. Our study shows that the HfOx resistive-switching memory is a promising candidate for next-generation nonvolatile memory device applications.

Charge trapping characteristics of atomic-layer-deposited HfO2 films with Al2O3 as a blocking oxide for high-density non-volatile memory device applications

Charge trapping characteristics of high-relative permittivity (high-?) HfO2 films with Al2O3 as a blocking oxide in p-Si/SiO2/HfO2/Al2O3/metal memory structures have been investigated. All high-? films have been grown by atomic layer deposition. A transmission electron microscope image shows that the HfO2 film is polycrystalline, while the Al2O3 film is partially crystalline after a high temperature annealing treatment at 1000 ?C for 10 s in N2 ambient. A well-behaved counter-clockwise capacitance?voltage hysteresis has been observed for all memory capacitors. A large memory window of ~7.4 V and a high charge trapping density of ~1.1 ? 1013 cm?2 have been observed for high-? HfO2 charge trapping memory capacitors. The memory window and charge trapping density can be increased with increasing thickness of the HfO2 film. The charge loss can be decreased using a thick trapping layer or thick tunnelling oxide. A high work function metal gate electrode shows low charge loss and large memory window after 10 years of retention. High-? HfO2 memory devices with high-? Al2O3 as a blocking oxide and a high work function metal gate can be used in future high-density non-volatile memory device applications.

TaOx-based resistive switching memories: prospective and challenges.

Resistive switching memories (RRAMs) are attractive for replacement of conventional flash in the future. Although different switching materials have been reported; however, low-current operated devices (<100 μA) are necessary for productive RRAM applications. Therefore, TaOx is one of the prospective switching materials because of two stable phases of TaO2 and Ta2O5, which can also control the stable low- and high-resistance states. Long program/erase endurance and data retention at high temperature under low-current operation are also reported in published literature. So far, bilayered TaOx with inert electrodes (Pt and/or Ir) or single layer TaOx with semi-reactive electrodes (W and Ti/W or Ta/Pt) is proposed for real RRAM applications. It is found that the memory characteristics at current compliance (CC) of 80 μA is acceptable for real application; however, data are becoming worst at CC of 10 μA. Therefore, it is very challenging to reduce the operation current (few microampere) of the RRAM devices. This study investigates the switching mode, mechanism, and performance of low-current operated TaOx-based devices as compared to other RRAM devices. This topical review will not only help for application of TaOx-based nanoscale RRAM devices but also encourage researcher to overcome the challenges in the future production.

Nanocrystals for silicon-based light-emitting and memory devices

Nanocrystals (NCs), representing a zero-dimensional system, are an ideal platform for exploring quantum phenomena on the nanoscale, and are expected to play a major role in future electronic and photonic devices. Here we review recent progress in the growth, characterization and utilization of some group-IV semiconductors (Si and Ge), metal and high-k NCs for silicon planar technology compatible light-emitting and floating gate memory devices. We first introduce the size-dependent electrical and optical properties of Si and Ge NCs. We outline some of the schemes to achieve light emission from indirect band gap Si and Ge NCs embedded in different high band gap oxide matrices. In particular, special emphasis is given on the review of the advances in Ge NCs because of some of their intriguing electronic and optical properties. We then describe the use of semiconductor and metal NCs as floating gates for non-volatile memory devices to achieve high data retention and faster program/erase speeds. The exploitation of high-k oxides with tunable and variable injection barriers for improved charge storage devices is discussed. Finally, the integration of single and multilayer metallic NCs and multilayer high-k oxides as floating gates is explored by the fabrication and testing of memory transistors.

Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs

The flicker noise characteristics of strained-Si nMOSFETs are significantly dependent on the gate oxide formation. At high temperature (900/spl deg/C) thermal oxidation, the Si interstitials at the Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and enhanced the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si nMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700/spl deg/C) tetraethylorthosilicate gate oxide. The capacitance-voltage measurements of the strained-Si devices with thermal oxide also show that the Si/oxide interface trap density increases and the Si-SiGe heterojunction is smeared out due to the Ge outdiffusion.

Mechanically strained strained-Si NMOSFETs

The drain-current enhancement of the mechanically strained strained-Si NMOSFET device is investigated for the first time. The improvements of the drain current are found to be /spl sim/3.4% and /spl sim/6.5% for the strained-Si and control Si devices, respectively, with the channel length of 25 /spl mu/m at the external biaxial tensile strain of 0.037%, while the drain-current enhancements are /spl sim/2.0% and /spl sim/4.5% for strained-Si and control Si devices, respectively, with the channel length of 0.6 /spl mu/m. Beside the strain caused by lattice mismatch, the mechanical strain can further enhance the current drive of the strained-Si NMOSFET. The strain distribution due to the mechanical stress has different effect on the current enhancement depending on the strain magnitude and channel direction. The smaller current enhancement for strained-Si device as compared to the control device can be explained by the saturation of mobility enhancement at large strain.

Band offsets and charge storage characteristics of atomic layer deposited high-k HfO2∕TiO2 multilayers

The band offsets and charge storage characteristics of atomic layer deposited high-k HfO2∕TiO2 multilayers with ten periods in p-Si∕SiO2∕(HfO2∕TiO2)∕Al2O3 structure have been investigated. The thickness of high-k HfO2 or TiO2 film is ∼0.5nm for each layer, before and after annealing treatment of 900°C for 1min in N2 ambient. High-resolution transmission electron microscopy, x-ray photoelectron spectroscopy, and ultraviolet photoelectron spectroscopy measurements on high-k HfO2∕TiO2 multilayers confirm the layer-by-layer structure after annealing treatment, suggesting the HfO2∕TiO2 multilayer quantum wells. The valence band offsets of HfO2 and TiO2 films are found to be ∼3.1 and ∼1.5eV, respectively. The conduction band offsets are found to be ∼1.7eV for HfO2 films and ∼0.9eV for TiO2 films. The high-k HfO2∕TiO2 multilayers in p-Si∕SiO2∕(HfO2∕TiO2)∕Al2O3/aluminum memory capacitor show a large capacitance-voltage hysteresis memory window of ∼5V at gate voltage of ±5V, due to the charge storage in multilayer...

Repeatable unipolar/bipolar resistive memory characteristics and switching mechanism using a Cu nanofilament in a GeOx film

This paper investigates the repeatable unipolar/bipolar resistive switching memory characteristics in a copper/germanium-oxide/tungsten (Cu/GeOx/W) structure. The switching mechanism occurs because of the lower barrier height for hole injection rather than electron injection. Therefore, Cu ions, as a positive charge, migrate before initiating growth at the GeOx/W interface and dissolving at the GeOx/Cu interface. The diameter of the Cu nanofilament increases linearly from 0.13 A to 25 nm as current compliances increase from 1 nA to 10 mA, as calculated using the other approach. The crystalline Cu nanofilament was also confirmed by high-resolution transmission electron microscopy analysis under SET. Good data retention with high resistance ratios of 102–105 (and >104 at 85 °C) and ∼109 was obtained under the bipolar and unipolar modes, respectively. Therefore, a maximum memory size of 5000 Pbit/in2 can be designed in the future.

Package-strain-enhanced device and circuit performance

The hole mobility enhancement can be as high as /spl sim/18% for SiO/sub 2/ and /spl sim/20% for high-k HfO/sub 2/ gate stack dielectrics with the uniaxial compressive strain (0.2%) parallel to the channel. The highest drain current of /spl sim/22% at saturation and /spl sim/30% at linear region is observed for the bulk Si PMOS with high-k gate stacks. The drain current and hole mobility of bulk Si PMOS are degraded under the small biaxial tensile strain, while substrate-strained Si device displays the opposite. The nonoptimized ring oscillator has the speed enhancement of /spl sim/7% under the uniaxial tensile strain parallel to NMOS channel. Proper package strain also gives the drive-current as well as mobility enhancement at 100/spl deg/C.

Excellent resistive memory characteristics and switching mechanism using a Ti nanolayer at the Cu/TaOx interface

Excellent resistive switching memory characteristics were demonstrated for an Al/Cu/Ti/TaOx/W structure with a Ti nanolayer at the Cu/TaOx interface under low voltage operation of ± 1.5 V and a range of current compliances (CCs) from 0.1 to 500 μA. Oxygen accumulation at the Ti nanolayer and formation of a defective high-κ TaOx film were confirmed by high-resolution transmission electron microscopy, energy dispersive X-ray spectroscopy, and X-ray photo-electron spectroscopy. The resistive switching memory characteristics of the Al/Cu/Ti/TaOx/W structure, such as HRS/LRS (approximately 104), stable switching cycle stability (>106) and multi-level operation, were improved compared with those of Al/Cu/TaOx/W devices. These results were attributed to the control of Cu migration/dissolution by the insertion of a Ti nanolayer at the Cu/TaOx interface. In contrast, CuOx formation at the Cu/TaOx interface was observed in an Al/Cu/TaOx/W structure, which hindered dissolution of the Cu filament and resulted in a small resistance ratio of approximately 10 at a CC of 500 μA. A high charge-trapping density of 6.9 × 1016 /cm2 was observed in the Al/Cu/Ti/TaOx/W structure from capacitance-voltage hysteresis characteristics, indicating the migration of Cu ions through defect sites. The switching mechanism was successfully explained for structures with and without the Ti nanolayer. By using a new approach, the nanoscale diameter of Cu filament decreased from 10.4 to 0.17 nm as the CC decreased from 500 to 0.1 μA, resulting in a large memory size of 7.6 T to 28 Pbit/sq in. Extrapolated 10-year data retention of the Ti nanolayer device was also obtained. The findings of this study will not only improve resistive switching memory performance but also aid future design of nanoscale nonvolatile memory.