G. Sai Saravanan

Ohmic contacts to pseudomorphic HEMTs with low contact resistance due to enhanced Ge penetration through AlGaAs layers

AuGe/Ni ohmic contacts are used as source and drain electrodes of pseudomorphic HEMTs (pHEMTs). High alloying temperatures are generally believed to be necessary to enhance penetration of the alloy materials through the AlGaAs layers in order to establish a very low resistance path for the source–drain currents to access the two-dimensional electron gas (2DEG) layer. Here we have performed alloying experiments in the temperature range of 390–450 °C, and the contact resistance was determined using transfer length method measurements. Germanium diffusion was studied using backside secondary ion mass spectrometry. During our study, we have observed that doping of the channel by germanium is possible even at lower temperatures. But alloying at lower temperatures does not appreciably enhance the concentration throughout the different device layers below the contact pads. Hence, unlike MESFET alloying, higher alloying temperatures are essential for increasing the doping concentration so as to reduce the contact resistance and overcome the resistance of the AlGaAs layers.

ELECTROMAGNETIC SIMULATION AND CHARACTERIZATION A METAL CERAMIC PACKAGE FOR PACKAGING OF HIGH ISOLATION SWITCHES

Packaging of planar MMICs poses a unique challenge at microwave frequencies as the dimensions of the encapsulating cavity are comparable to wavelength at the operational frequencies. In addition, the efiect of ground loops (caused by bond wires exposed to ground over extended length due to gaps between interconnects) deteriorates the situation even further in circuits like MMIC switches requiring high isolation between ports. The ground loops cause re∞ections thereby deteriorating the insertion loss flgure of merit. This paper presents optimization of design of a metal ceramic package used for packaging an SPDT MMIC switch working in the frequency range of 5{6GHz. The microwave performance of the package was simulated using EM simulation with parameters including cavity dimensions, port placement, gaps between interconnect lines, package feed-thrus and MMIC chip pads. Detailed characterization of the bare package and packaged SPDT MMIC done later shows a good match between the simulated and measured performance. The SPDT MMIC performance degradation was arrested by improvement in the package structure and it showed insertion loss of i1.6dB and input/output (I/O) return losses of »16dB in the new package as compared to the values of i2.1dB insertion loss and i12dB I/O return losses in the original package. The port-to-port isolation remained unchanged (»40dB in both cases) as it is governed by the MMIC assembly inside the package rather than the conditions at the I/O interfaces in this kind of large sized packages.

Influence of activation of Si29+ ion-implantation in GaAs on ohmic contact resistance and electrical performances of MESFETs

The active layers of Metal Semiconductor Field Effect Transistors (MESFETs) are obtained by Si29+ ion implantation in GaAs. Implantation was done at 35 keV with a higher dose near the wafer surface for facilitating easier formation of ohmic contacts, and at 180 keV with a lower dose for obtaining the device channel. Post-implantation annealing was carried out in a rapid thermal processor for activating the implants. Very high activation levels of about 60% for the n+ GaAs layer, and 85% for the n-GaAs channel layer were achieved by annealing at 955 °C for 25 s. Activation was characterized using C–V profiling, secondary ion mass spectrometry and by electrical device data of fabricated MESFETs. We attempt an experimental correlation between the ohmic contact resistance (R c) and activation of both the n+ and the channel layer. It was found that very high and simultaneous activation of the n+ and channel layers results in very low contact resistances. The conduction of source-drain current into the channel is easily facilitated due to reduction in the resistance of the transition region at the interface of n+-contact and n-channel layers.

Reliability studies of AuGe/Ni/Au ohmic contacts to MESFETs by accelerated thermal aging tests

Optimally alloyed AuGe/Ni/Au source-drain ohmic contacts to MESFETs with very low contact resistance (Rc) of the order 0.05 - 0.07 Omega-mm were obtained after rapid thermal alloying at 400degC. We have studied the degradation of ohmic contacts at elevated temperatures for 4000 hours. Ohmic contact test structures were subjected to accelerated life test temperatures at 185degC, 200degC and 230degC. We found that the drifts in Rc of the optimally alloyed contacts after thermal aging were as low as +13%, which are possibly one of the lowest drifts reported hitherto. This low drift may be due to the formation of thermally stable compounds and their nature at the ohmic contact interfaces, and the access regions during optimum alloying.

Design and Electrical Characterization of Wafer-level Micro-package for GaAs-based RFMEMS Switches

Abstract Packaging of Micro-Electro-Mechanical system (MEMS) at wafer-level is one of the critical areas for its application, as the MEMS elements are delicate and can easily get damaged during wafer scribing or packaging process. We describe here a novel approach for wafer-level encapsulation of GaAs-based RFMEMS switches. EM simulation of the proposed microcaps has been carried out to study the effect of encapsulation on the switch performance. Both GaAs and Pyrex glass-based caps have been fabricated and the switches were encapsulated. The performance of the packaged switches has been characterized and the measured results show a close agreement with EM simulation.

Gate recess structure engineering using silicon-nitride-assisted process for increased breakdown voltage in pseudomorphic HEMTs

We report the fabrication of pseudomorphic high electron mobility transistors (pHEMTs) with engineered recess structure of any width of choice, by a single lithography and etching step with the help of silicon-nitride-assisted process. In this process, a silicon nitride layer is deposited prior to gate lithography. First, the silicon nitride is etched by buffered hydrofluoric acid (BHF) in the gate opening and then selective recessing is performed. The recess base width can be engineered by varying etch time of silicon nitride in BHF. The base width increases linearly with etch time as shown by SEM. We demonstrate that the top photoresist gate opening that decides the gate length is unaffected by any duration of silicon nitride etch time. Thereby, we have engineered the distance from gate edge to n+-GaAs (Lgn+) which decides the gate-to-drain breakdown voltage (BVgd). With this method, BVgd?increased from 12 to 20?V as a function of Lgn+. The electric field distribution across the recess structure has been simulated to interpret this result. Since the high BVgd?of pHEMT is essential for power applications as well as switch applications, this method can be easily adopted even though the corresponding reduction in transconductance and unit current gain cut-off frequency (ft) is only marginal from 375 to 350 mS mm?1?and from 39 to 31?GHz, respectively.

Bias dependent and scalable small-signal modeling of pseudomorphic HEMTs

Results of small-signal modeling of 0.5um gate length pseudomorphic HEMTs are presented here. Modeling included scalability with respect to number of gate fingers, gate width and gate bias dependence of Equivalent Circuit Parameters (E.C.Ps). p-HEMTs with gate widths of 100 µm and 150 µm, each with varying number of gate fingers (2, 4, 6) keeping all other structural parameters constant were fabricated for this study. To find small-signal E.C.Ps we used method proposed by Dambrine et.al. [2] and White-Healy [3]. On-wafer measurement of S-parameters for all devices was done from 100 MHz to 40 GHz under different bias-conditions. Using this data, all the E.C.Ps were then extracted for each device, at various gate-biases and Vds = 3V. Finally we have a model that can give the E.C.Ps of any device we fabricated, given the gate-bias, number of gate-fingers and gate-width. This equivalent circuit can be used to generate S-parameters of devices with good accuracy in the whole frequency range of measurement.

Gate recess structure engineering in MESFETs to achieve higher schottky breakdown voltage for switch MMIC applications

In this paper we report for the first time, a method of generating wide gate recess structure in single recess step by the help of a bi-layer lithography technique, which can be used to generate varying gate recess width by varying developmental time. It is established that the gate recess structure decides the schottky breakdown voltages in these devices. The distance from gate edge-to-n+ in the recess structure becomes very critical for high Vb. Commonly, double recessing is used to achieve this, which is more complicated. We have achieved Vb as high as 20Volts using single recess.

Optimization of pulse reversal electrodeposition with fine grains and low roughness for GaAs RF MEMS structures

GaAs MESFET-based switches suffer from high insertion losses. As an alternative, GaAs RF MEMS have shown great promise due to high isolation, low insertion losses, and wide bandwidths. Some factors constraining the fabrication have been suitable planarization techniques, quality of metallisation, stress in the beams, and elimination of stiction of beams to the central signal electrode. Quality of metallisation makes pulse reversal plating technique viable for production compared to DC plating. Coplanar waveguide pads, anchors, and beams are formed using this process. This paper discusses the optimization of pulse reversal electrodeposition process to fabricate different stages of RF MEMS switches.

Study of selective gate recess etching of InGaAs/InAlAs/InGaAs metamorphic HEMT structures using succinic acid based etchant

Metamorphic HEMTs on GaAs substrates are promising devices of today as they are operated at even higher frequencies for microwave applications compared to pseudomorphic HEMTs. The selective removal of n+ InGaAs ohmic contact layer from the top of the device structure poses a major challenge during fabrication. We have studied the influence of temperature on the selectivity of etch rate between the n+ InGaAs and underlying InAlAs layers using succinic acid based etchant. The etchant was composed of succinic acid solution mixed with hydrogen peroxide and deionized water. The pH of the solution was adjusted to 5 by adding NH4OH. The etch rates at different temperatures between 14degC to 30degC were estimated by profiling the etched pattern using atomic force microscopy (AFM). Surface roughness of the etched area also was studied using AFM. It was found that the selectivity has improved with temperature. This is possibly due to simultaneous occurrence of low etch rates of InAlAs due to presence of aluminum oxide and high etch rates of InGaAs due to increased temperature. It was also found that the surface roughness was higher at lower temperatures contrary to the observations made in the case of pseudomorphic HEMTs.