Un-Ku Moon

Background calibration techniques for multistage pipelined ADCs with digital redundancy

The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A high-accuracy calibration is achieved by recalculating the digital output based on each stages equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A two-channel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16-bit linearity can be achieved after calibration for an ADC with /spl sigma/=0.1% capacitor mismatches and 60 dB opamp gain.

Background digital calibration techniques for pipelined ADCs

A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADCs) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDACs) commonly used in multistep or pipelined ADCs. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other self-calibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of self-calibrating multistep or pipelined ADCs. The proposed method improves the performance of the inherently fast ADCs by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, of amp DC gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a split-reference injection technique. Ultimately, the missing signal within two-thirds of the Nyquist bandwidth is recovered with 16-b accuracy using a forty-fourth order polynomial interpolation, behaving essentially as an FIR filter,.

A CMOS self-calibrating frequency synthesizer

A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described. In fully integrated PLLs, the VCO output frequency should be tunable over a wide range of frequencies, covering the desired range of the synthesizer output frequencies, for all processing variations and operating conditions. A wide tuning range realized by making the VCO gain K/sub o/ large has the unwanted effect of increasing the phase noise at the output of the VCO, and hence the PLL as well. In this work, the wide tuning range is realized by digital control, with process variability managed through self-calibration. The PLL is only required to pull the oscillator output frequency to account for the digital quantization, temperature variations, and some margin. This allows the K/sub o/ to be small, with better noise performance resulting. The prototype self-calibrating frequency synthesizer, capable of operating from 80 MHz to 1 GHz, demonstrates a measured absolute jitter of 20-ps rms at 480-MHz operating frequency. The prototype IC is fabricated in a 0.35-/spl mu/m 3-V digital CMOS process.

Analysis of charge-pump phase-locked loops

In this paper, we present an exact analysis for third-order charge-pump phase-locked loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the z-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and s-domain analysis is provided. The effect of the loop parameters and the reference frequency on the loop phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE.

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL

Adaptive digital correction of analog errors in MASH ADCs. II. Correction using test-signal injection

For pt. I see ibid., vol. 47, no. 7, p. 621-8 (2000). This part describes a different adaptation strategy. It relies on the injection of a pseudorandom two-level test signal at the input of the first-stage quantizer, where it is added to the quantization noise. The test signal then leaks into the output signal, where it can be detected and used to control the digital noise-cancellation filter. This paper describes the correction process, as well as some efficient structures for implementing it, and demonstrates the effectiveness of the technique by describing three design examples.

A Wide-Tracking Range Clock and Data Recovery Circuit

A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 mum CMOS process achieves BER <10-12 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking.

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-/spl mu/m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm/sup 2/ of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline.

An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain

Correlated level shifting (CLS) is introduced as a new switched-capacitor technique to provide true rail-to-rail performance while reducing errors from finite opamp gain. There is negligible kT/C noise increase and in many cases a speed advantage compared to using a high gain opamp. The gain enhancement is quantified with formulas and the general technique is compared to correlated double sampling (CDS). Results are presented from a 0.18 mum CMOS testchip of a 20 MHz, 12-bit pipelined A/D converter using CLS to reduce errors from finite opamp dc gain and limited opamp swing. It achieves 10.5 ENOB operating beyond the supply rails using an opamp circuit with 30 dB loop gain and 0.9 V supply.

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mm/sup 2/ using a 0.35-/spl mu/m CMOS technology.