Gabriel M. Silberman

An architectural framework for supporting heterogeneous instruction-set architectures

An architectural framework that allows software applications and operating system code written for a given instruction set to migrate to different, higher performance architectures is described. The framework provides a hardware mechanism that enhances application performance while keeping the same program behavior from a user perspective. The framework is designed to accommodate program exceptions, self-modifying code, tracing, and debugging. Examples are given for IBM System/390 operating-system code and AIX utilities, showing the performance potential of the scheme using a very long instruction word (VLIW) machine as the high-performance target architecture.<<ETX>>

An architectural framework for migration from CISC to higher performance platforms

We describe a novel architectural framework that allows software applications written for a given Complex Instruction Set Computer (CISC) to migrate to a different, higher performance architecture, without a significant investment on the part of the application user or developer. The framework provides a hardware mechanism for seamless switching between two instruction sets, resulting in a machine that enhances application performance while keeping the same program behavior (from a user perspective). High execution speed on migrated applications is achieved through automated translation of the object code of one machine to that of the other, using advanced global optimization and scheduling techniques. Issues affecting application behavior, such as precise exceptions, as well as self-modifying code, are addressed. Relaxation of full compatibility on these issues lead to further possible performance gains, encouraging applications to adopt the newer architecture. The proposed framework offers a path for moving from complex instruction set computers (CISCs) to newer architectures, such as reduced instruction set computers (RISCs), superscalars, or very long instruction word (VLIW) machines, while protecting the extensive economic investment represented by existing software. To illustrate our approach, we show how system code written (and compiled) for the IBM System/390 can yield fine-grain parallelism, as it is targeted for execution by a VLIW machine, with encouraging performance results.

VLIW compilation techniques in a superscalar environment

We describe techniques for converting the intermediate code representation of a given program, as generated by a modern compiler, to another representation which produces the same run-time results, but can run faster on a superscalar machine. The algorithms, based on novel parallelization techniques for Very Long Instruction Word (VLIW) architectures, find and place together independently executable operations that may be far apart in the original code. i.e., they may be separated by many conditional branches or belong to different iterations of a loop. As a result, the functional units in the superscalar are presented with more work that can proceed in parallel, thus achieving higher performance than the approach of using hardware instruction dispatch techniques alone. While general scheduling techniques improve performance by removing idle pipeline cycles, to further improve performance on a superscalar with only a few functional units requires a reduction in the pathlength. We have designed a set of new algorithms for reducing pathlength and removing stalls due to branches, namely speculative load-store motion out of loops, unspeculation, limited combining, basic block expansion, and prolog tailoring. These algorithms were implemented in a prototype version of the IBM RS/6000 xlc compiler and have shown significant improvement in SPEC integer benchmarks on the IBM POWER machines. Also, we describe a new technique to obtain profiling information with low overhead, and some applications of profiling directed feedback, including scheduling heuristics, code reordering and branch reversal.

Simulating Pass Transistor Circuits Using Logic Simulation Machines

An algorithm for pass transistor simulation using the Yorktown Simulation Engine (YSE) is outlined. Implementing this algorithm yields an efficient tool for custom VLSI circuit design verification and fault simulation. Modeling of circuits under this environment is defined, including the analysis of the algorithms performance for some general circuit types. A number of specific examples are discussed in detail.

Overview: the centre for advanced studies

The Centre for Advanced Studies (CAS) was founded in 1990 to facilitate the transfer of research ideas into products. This essay describes the original goals of CAS, how they have been applied, and how they have evolved. CAS has successfully moved concepts into products, matched students with appropriate jobs, demonstrated IBMs commitment to leadership by integrating current research into products available to customers, and supported academic research by doctoral students and faculty from more than 30 universities. More than 150 professors have received CAS funds. As we move into our eighth year, CAS is poised to expand beyond North America and to involve additional IBM sites.

Fast Pass-Transistor Simulation for Custom MOS Circuits

This approach uses the Yorktown Simulation Engine to bridge the gap between electrical and gate-level simulators. It is well-suited to fault simulation and design verification.

A backtracing-oriented procedure for the analysis of combinational gate-level designs

Abstract We present an approach to the analysis of combinational gate-level designs, which produces information conducive to the acceleration of the backtracing process, pervasive in automatic test pattern generation algorithms. This analysis yields information which can be used to make intelligent decisions within the search space spanned by the backtracing process. A procedure which embodies this approach is presented, together with experimental results.