Leendert M. Huisman

Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm

A new way of diagnosing ICs that fail logic tests is described. It can handle bridging fault, opens, transition faults and many more complex defects as easily and as accurately as regular stuck-at faults.

Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)

A new form of logic diagnosis is described that is suitable for diagnosing fails in combinational logic. It can diagnose defects that can affect arbitrarily many elements in the integrated circuit. It operates by first identifying patterns during which only one element is affected by the defect, and then diagnosing the fails observed during the application of such patterns, one pattern at a time. Single stuck-at faults are used for this purpose, and the aggregate of stuck-at fault locations thus identified is then further analyzed to obtain the most accurate estimate of the identities of those elements that can be affected by the defect. This approach to logic diagnosis is as effective as that of classical stuck-at fault-based diagnosis, when the latter applies, but is far more general. In particular, it can diagnose fails caused by bridges and opens as well as fails caused by regular stuck-at faults.

A small test generator for large designs

We report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. the fraction of faults that are resolved, are comparable to or better than those reported previously in the literature. No preprocessing is required and the amount of memory needed is less than 100 bytes per gate. The low memory requirements and high performance have been achieved by working with a larger but simpler search space, by simplifying decision making and backtracking and by using only implication techniques that are fast and that require no preprocessing.

Data mining integrated circuit fails with fail commonalities

We describe ways to use fail data from many failing integrate circuits (ICs) to determine which ICs failed because of similar causes, rather than to determine the cause of each individual failing IC. The purpose of finding clusters of similarly failing ICs is to focus on systematic defects, and to de-emphasize random ones. Once large groups of similarly failing ICs have been identified, a selection of the ICs in each group can be diagnosed using standard diagnostic routines.

SLS-a fast switch-level simulator (for MOS)

SLS, a large-capacity, high-performance switch-level simulator developed to run on an IBM System/370 architecture is described. SLS uses a model which closely reflects the behavior of MOS circuits. The high performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady-state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage. >

Diagnosis and characterization of timing-related defects by time-dependent light emission

Technological advances such as flip-chip packaging, multiple hierarchical wiring planes, and ultra-high frequencies reduce the effectiveness of conventional diagnostic techniques. It has recently been demonstrated that light pulses emitted during circuit switching can be used to characterize the behaviour of integrated circuits. In this paper, a new method of circuit characterization using this technique is described. An example of the diagnosis of a timing failure caused by a resistive path to a single transistor is described.

SLS - A Fast Switch Level Simulator for Verification and Fault Coverage Analysis

We describe SLS, a large capacity, high performance switch level simulator, developed to run on an IBM System/370 architecture, that uses a model which closely reflects the behavior of MOS circuits. This performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage.

Simulating Pass Transistor Circuits Using Logic Simulation Machines

An algorithm for pass transistor simulation using the Yorktown Simulation Engine (YSE) is outlined. Implementing this algorithm yields an efficient tool for custom VLSI circuit design verification and fault simulation. Modeling of circuits under this environment is defined, including the analysis of the algorithms performance for some general circuit types. A number of specific examples are discussed in detail.

The effect on quality of non-uniform fault coverage and fault probability

This paper addresses problems associated with the production and interpretation of traditional fault coverage numbers. The first part addresses the issue of non-uniform distribution of detected faults. It is shown that there is a large difference in final quality between covering the chip all over and leaving parts relatively untested, even if the coverage is the same in both cases. The second part deals with the use of weighted, rather than unweighted fault coverages and investigates the use of readily-available extracted capacitance information to produce a weighted fault coverage which is more useful for producing quality estimates, without having to perform a full defect analysis. Results show significant differences in weighted versus unweighted coverages, and also that these differences can be in either direction.

The reliability of approximate testability measures

Techniques for gauging the accuracy of approximate testability measures that estimate the random-pattern testability of gate-level faults in designs with combinational logic are considered. The measures examined are overall fault-exposure distribution, high coverage, and fault grading. Sampling techniques are compared with the Stafan and Protest approximate testability measures. For random-pattern testing, it is clear that state-of-the-art testability measures like Stafan and Protest do provide some information about the testability of single faults or complete designs, but this information is not accurate; in many areas of use they cannot compete with carefully chosen sampling techniques. The three techniques described here are applicable to testing strategies other than the random-pattern testing of stuck-at faults; they are equally useful in a weighted random-pattern testing environment, for example.<<ETX>>