Gabriele Minoia

A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies

Silicon photonics platforms are emerging as attractive solutions for low power and cost effective short/medium-reach optical interconnects. To overcome the intrinsic limitations of monolithically integrated photonics with electronics, STMicroelectronics has developed a 3D-compatible silicon photonics platform that implements in the FEOL only optical devices. Photonics Integrated Circuits are made compatible with 3D assembly of Electronic Integrated Circuits through the use of copper pillars. In this paper we present a 25Gbps Opto-Electronic receiver operating at 1310nm wavelength, consisting of an integrated waveguide Germanium photodiode interfaced by means of copper pillars to a 65nm CMOS amplification chain. The receiver demonstrates an Average Optical Power sensitivity at photodiode input, at a BER of 10-12, of -11.9dBm with a PRBS7 input signal, corresponding to a 97μApp TIA input current. The achieved sensitivity is ~6dB better than state-of-the-art monolithically integrated silicon photonics receivers, at comparable TIA and LA power consumption.

22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s

In this scenario, this work presents a complete 25Gb/s silicon photonics electro-optical transmitter front-end comprising an MZM, using carrier depletion P-N junctions and operating at 1310nm wavelength, and a power-efficient CMOS driver. The transmitter optical path is integrated on STMicroelectronics 3Dcompatible silicon-photonics platform (PIC25G), which implements only optical devices in the front-end of line (FEOL) [4]. The electronic IC, realized in 65nm bulk CMOS technology, is 3D-assembled on top of the photonic IC by means of 20μm-diameter copper pillars, minimizing the interconnection parasitic capacitance. This 1310nm 25Gb/s silicon photonics electro-optical transmitter reports error-free operation with wide open optical eye diagrams at a competitive dynamic extinction ratio (ER) of up to 6dB using a depletion-mode MZM.

Insights Into Silicon Photonics Mach–Zehnder-Based Optical Transmitter Architectures

Mach-Zehnder-based modulator architectures lend themselves to the realization of high-data-rate Silicon Photonics transmitters. In this work the challenges set by the integration of such devices on silicon are analyzed in depth. The two main alternative electronic driver architectures, namely multistage and travelling wave, are compared with focus to power efficiency. This is, in fact, a key parameter when considering the stringent requirements of standard module form factors. A 25 Gbps multistage and a 56 Gbps travelling wave modulator have been realized. Each electro-optical transmitter is obtained by the 3D assembly of an electronic IC on top of a photonic IC through copper pillars. STMicroelectronics PIC25G Silicon Photonics platform has been adopted for the fabrication of optical devices, while 65 nm CMOS and 55 nm BiCMOS technologies are exploited to realize the electronic drivers. A 30% better power efficiency compared to Silicon Photonics state-of-the-art at similar data rates and comparable extinction ratio performance has been demonstrated in both cases. Since packaging is also a crucial aspect for Silicon Photonics high volume production, experiments on bare dice as well as on packaged chips are reported.

23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies

The ever-increasing data center IP traffic, up to 8.6 zettabytes per year by 2018 with nearly 3× growth since 2013 [1], requires power-efficient high-speed interconnects. Next generation optical interfaces will adopt 50Gbaud signaling [2], and minimizing power consumption is key to enable the use of small form-factor optical modules for electro-optical conversion. In this perspective, silicon photonics is an attractive alternative to discrete photonics, lending itself to higher miniaturization at reduced cost [3]. Furthermore, silicon photonics enables co-design of electronics with photonics, thus optimizing transceiver power efficiency. In particular, the electro-optical transmitter constitutes the main source of power consumption. Travelling wave Mach-Zehnder modulator (MZM) architectures are used in discrete photonics realizations as data rate increases, and lend themselves to silicon photonics. However silicon photonics suffers from electrical propagation losses and bandwidth limitations of integrated transmission lines, requiring equalization in the electronic driver to address 50Gbaud operation at moderate consumption and also in advanced node technologies. In this work, we employ a bifilar transmission line determining an electrical propagation loss of ~3dB/mm at 28GHz. Using an equalizer counteracts its effect, applying passive boost and shunt peaking in the pre-driving stage, combined with passive peaking in the load coupling. A 75% increase in the vertical aperture of the optical eye diagram is thus achieved with no power consumption penalty due to the equalizer. The complete electro-optical transmitter, operating at 56Gb/s at 1310nm wavelength, dissipates 300mW and ensures an extinction ratio (ER) higher than 2.5dB. This 56Gb/s silicon photonics transmitter displayes more than 30% power savings with respect to the state-of-the-art [4].

A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links

A 25Gb/s silicon photonics receiver comprising an Electronic Integrated Circuit and a Photonic Integrated Circuit fabricated in 65nm CMOS and in PIC25G technologies respectively is presented. The two chips are 3D-integrated using copper pillars. The front-end amplifier introduces low-noise techniques, realizing record-low input-referred noise current of 0.91pArms, leading to the highest sensitivity (OMA = −11.3dBm) among 25Gb/s silicon photonics receivers reported to date.

Transmitter Made up of a Silicon Photonic IC and its Flip-Chipped CMOS IC Driver Targeting Implementation in FDMA-PON

We report on the design, fabrication, and characterization of a reflective transmitter targeting implementation in passive optical networks (PON) with frequency division multiplexed access (FDMA). It is made up of a Silicon photonic integrated circuit (Si-PIC) comprising a reflective Mach Zehnder modulator and its flip-chipped CMOS electronic integrated circuit driver, the two ICs being interconnected by means of high density and low parasitic copper micro pillars. Several transmissions, in an FDMA PON context, are successfully demonstrated using 500 MBaud QPSK and 16-QAM modulated subcarriers, achieving bit error rate below 2.10-3. For QPSK-modulated subcarriers (respectively, 16-QAM), the available access frequency bandwidth is measured to be 1-7 GHz (respectively, 2-4 GHz) with an available loss budget of 9 dB (respectively, 5 dB). Improvements of the Si-PIC are further identified to achieve compliancy with 31 dB ODN loss.

A 5 th order g m -C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS

A 5th order gm-C filter complete with calibration circuits with wide tuning range and cut-off frequency up to the GHz range is presented. To simplify calibrations, integrators are designed to have a relatively low static gain of 32dB, regulated with negative resistors. Transconductance and gain are continuously controlled with a master-slave approach leading to a remarkably stable filter shape and cut-off frequency accuracy within ±3% over a 0°-100° temperature range and ±5% supply variation. A test-chip has been realized in a 28nm Low Power CMOS technology. The cut-off frequency is tunable from 220MHz to 3.3GHz with power dissipation scaling from 5mW to 30mW. THD is -40dB at -24dBV input signal while the integrated input equivalent noise is lower than 400μVrms, corresponding to an SNR better than 39dB.

A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4

Shunt-feedback TIAs suffer from a trade-off between noise and bandwidth. In this work we propose a two stage 25Gb/s front-end, made of a low noise narrow-band TIA followed by an equalizer aimed at restoring the required bandwidth, providing a 4x noise power reduction compared to a traditional design approach. A 65nm receiver cascading the proposed front-end, the limiting amplifier and a buffer, tailored to 100GBASE-LR4, demonstrates a gain of 83dBΩ, an input referred equivalent rms noise current of 2.44μA and an electrical analog bandwidth tunable between 10.6GHz and 18.2GHz. The power consumption is 93mW with a FOM of 2066GHz·Ω/mW.

A fully packaged 25 Gbps/channel WDM photoreceiver module based on a Silicon Photonic Integrated Circuit and a flip-chipped CMOS quad transimpedance amplifier

Growing demand for bandwidth in Datacom optical links and High Performance Computers (HPC) has recently led to new optoelectronic modules based on Silicon Photonics Integrated Circuits [1]. One of the intrinsic capabilities of this technology is its scalability in terms of aggregated data rate, due to the possibility of combining Space Division Multiplexing, Wavelength Division Multiplexing, and the use of advanced modulation formats such as PAM4 or QPSK [2]. As a result, standard commercial modules using Silicon Photonics Integrated Circuits (Si-PIC), typically providing 10 to 25 Gbps (OOK) per channel over several singlemode fibers, will evolve up to and beyond 400 Gbps and more aggregated data rate in the coming years. In this paper, we demonstrate the introduction of Wavelength Division Multiplexing in a multichannel photoreceiver module using a Si-PIC, at a data rate of 25 Gbps per channel.