Daniele Baldi

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques

Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered for RF frequency synthesis. However, they suffer from intrinsic deficiencies making them inferior to traditional analog solutions. The investigation in this paper shows that in-band output spurs, the major shortcoming of wideband divider-less ADPLLs with respect to analog fractional PLLs, are intrinsic and due to the finite resolution of the time-to-digital converter (TDC), even assuming perfect quantization and linearity. Moreover, even if the conceptual spur level is arbitrarily reduced by increasing the TDC resolution, TDC nonlinearities can cause a significant spur re-growth. This paper proposes two techniques to reduce the gap between all-digital and analog implementations of wideband fractional PLLs. These techniques have been applied to a 3 GHz ADPLL, whose bandwidth is programmable from 300 kHz to 1.8 MHz, operating from a 25 MHz reference signal. The test chip features more than 10 dB of worst in-band spur reduction when both corrections are active, for a worst-case in-band spur of -45 dBc at a bandwidth of 1.8 MHz and an in-band noise floor of -101 dBc/Hz. The chip core occupies 0.4 mm2 in 65 nm CMOS technology, and consumes less than 10 mW from a 1.2 V supply.

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

Nonlinearities in the time-to-digital converter (TDC) are a significant source of fractional spurs in a divider-less fractional-N ADPLL. Using an abstract model for the TDC, this paper presents a dithering method which is mathematically shown to suppress fractional tones, in conjunction with a feedforward dither cancellation technique which suppresses dither-induced phase noise. A mostly-digital calibration algorithm is also presented which ensures consistent phase noise cancellation across PVT conditions. The aforementioned techniques are implemented in a 65 nm digital CMOS prototype running at 3.5 GHz from a 35 MHz reference. The ADPLL demonstrates - 101 dBc/Hz in-band phase noise at a bandwidth of 3.4 MHz, - 58 dBc worst fractional spurious performance across the entire fractional range, and consumes 8.7 mW from a 1.2 V supply.

A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction

This work introduces two techniques to ameliorate high-resolution TDC performance: a precise TDC calibration algorithm and a background mismatch correction algorithm. To demonstrate the proposed techniques we have realized a 3GHz fractional synthesizer based on an 8ps resolution TDC in standard 65nm CMOS. The prototype uses a 25MHz reference and consumes 9.5mW excluding test buffers. The bandwidth is programmable from 100kHz to 2MHz, in-band phase noise is -100dBc/Hz and the worst-case in-band spur, after correction, is -45dBc. This is the first prototype with low phase noise, spur suppression and wide-bandwidth known to the authors. Moreover, it is competitive with fractional-N analog PLLs.

A multi standard 1.5 to 10Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication

A 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS is presented. It is based on an adaptive 3-tap latch-based DFE data recovery with self-aligning capability and on an early-late digital clock recovery capable of SSC tracking. Extensive digital features allow self-calibration and eye analysis. The macro measures 0.3 mm2 and consumes 140 mA from 1 V at 8.5 Gb/s.

A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies

Silicon photonics platforms are emerging as attractive solutions for low power and cost effective short/medium-reach optical interconnects. To overcome the intrinsic limitations of monolithically integrated photonics with electronics, STMicroelectronics has developed a 3D-compatible silicon photonics platform that implements in the FEOL only optical devices. Photonics Integrated Circuits are made compatible with 3D assembly of Electronic Integrated Circuits through the use of copper pillars. In this paper we present a 25Gbps Opto-Electronic receiver operating at 1310nm wavelength, consisting of an integrated waveguide Germanium photodiode interfaced by means of copper pillars to a 65nm CMOS amplification chain. The receiver demonstrates an Average Optical Power sensitivity at photodiode input, at a BER of 10-12, of -11.9dBm with a PRBS7 input signal, corresponding to a 97μApp TIA input current. The achieved sensitivity is ~6dB better than state-of-the-art monolithically integrated silicon photonics receivers, at comparable TIA and LA power consumption.

22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s

In this scenario, this work presents a complete 25Gb/s silicon photonics electro-optical transmitter front-end comprising an MZM, using carrier depletion P-N junctions and operating at 1310nm wavelength, and a power-efficient CMOS driver. The transmitter optical path is integrated on STMicroelectronics 3Dcompatible silicon-photonics platform (PIC25G), which implements only optical devices in the front-end of line (FEOL) [4]. The electronic IC, realized in 65nm bulk CMOS technology, is 3D-assembled on top of the photonic IC by means of 20μm-diameter copper pillars, minimizing the interconnection parasitic capacitance. This 1310nm 25Gb/s silicon photonics electro-optical transmitter reports error-free operation with wide open optical eye diagrams at a competitive dynamic extinction ratio (ER) of up to 6dB using a depletion-mode MZM.

Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs

As technology pushes deeper into the nanoscale, the difficulty in developing high-performance analog functions has driven an explosion in digitally intensive architectures to replace them. Commonalities among these new architectures include a paradigm shift toward temporal versus voltage encoding of analog signals, and the extensive use of digital calibration. In particular, recent developments in fractional-N all-digital phase-locked loops (ADPLLs) have proven them to be competitive with analog state of the art for narrowband applications, demonstrating excellent phase noise and achieving even traditionally difficult standards such as GSM. However, to achieve comparable high performance for wideband applications requires a reduction in fractional spurs. This paper provides a brief summary of ADPLL architectures, leading to a prototype synthesizer at 3 GHz which implements a spurious tone reduction technique. Along the way, an efficient simulation model to predict fractional spur amplitude and frequency in ADPLLs is presented. The 3 GHz prototype operates from a flexible reference frequency, between 25 MHz-100 MHz, has in-band phase noise of -101 dBc/Hz with a decade of loop bandwidth programmability, and in-band spurs below -45 dBc. The synthesizer occupies 0.4 mm2 in 65 nm digital CMOS and consumes less than 10 mW from a 1.2 V supply.

Insights Into Silicon Photonics Mach–Zehnder-Based Optical Transmitter Architectures

Mach-Zehnder-based modulator architectures lend themselves to the realization of high-data-rate Silicon Photonics transmitters. In this work the challenges set by the integration of such devices on silicon are analyzed in depth. The two main alternative electronic driver architectures, namely multistage and travelling wave, are compared with focus to power efficiency. This is, in fact, a key parameter when considering the stringent requirements of standard module form factors. A 25 Gbps multistage and a 56 Gbps travelling wave modulator have been realized. Each electro-optical transmitter is obtained by the 3D assembly of an electronic IC on top of a photonic IC through copper pillars. STMicroelectronics PIC25G Silicon Photonics platform has been adopted for the fabrication of optical devices, while 65 nm CMOS and 55 nm BiCMOS technologies are exploited to realize the electronic drivers. A 30% better power efficiency compared to Silicon Photonics state-of-the-art at similar data rates and comparable extinction ratio performance has been demonstrated in both cases. Since packaging is also a crucial aspect for Silicon Photonics high volume production, experiments on bare dice as well as on packaged chips are reported.

23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies

The ever-increasing data center IP traffic, up to 8.6 zettabytes per year by 2018 with nearly 3× growth since 2013 [1], requires power-efficient high-speed interconnects. Next generation optical interfaces will adopt 50Gbaud signaling [2], and minimizing power consumption is key to enable the use of small form-factor optical modules for electro-optical conversion. In this perspective, silicon photonics is an attractive alternative to discrete photonics, lending itself to higher miniaturization at reduced cost [3]. Furthermore, silicon photonics enables co-design of electronics with photonics, thus optimizing transceiver power efficiency. In particular, the electro-optical transmitter constitutes the main source of power consumption. Travelling wave Mach-Zehnder modulator (MZM) architectures are used in discrete photonics realizations as data rate increases, and lend themselves to silicon photonics. However silicon photonics suffers from electrical propagation losses and bandwidth limitations of integrated transmission lines, requiring equalization in the electronic driver to address 50Gbaud operation at moderate consumption and also in advanced node technologies. In this work, we employ a bifilar transmission line determining an electrical propagation loss of ~3dB/mm at 28GHz. Using an equalizer counteracts its effect, applying passive boost and shunt peaking in the pre-driving stage, combined with passive peaking in the load coupling. A 75% increase in the vertical aperture of the optical eye diagram is thus achieved with no power consumption penalty due to the equalizer. The complete electro-optical transmitter, operating at 56Gb/s at 1310nm wavelength, dissipates 300mW and ensures an extinction ratio (ER) higher than 2.5dB. This 56Gb/s silicon photonics transmitter displayes more than 30% power savings with respect to the state-of-the-art [4].

A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links

A 25Gb/s silicon photonics receiver comprising an Electronic Integrated Circuit and a Photonic Integrated Circuit fabricated in 65nm CMOS and in PIC25G technologies respectively is presented. The two chips are 3D-integrated using copper pillars. The front-end amplifier introduces low-noise techniques, realizing record-low input-referred noise current of 0.91pArms, leading to the highest sensitivity (OMA = −11.3dBm) among 25Gb/s silicon photonics receivers reported to date.