Matteo Repossi

A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS

High-rate communications technology leveraging the unlicensed spectrum around 60 GHz is almost ready for deployment with several demonstrations of successful wireless links. One key aspect of the transceiver is the ability to handle analog fractional bandwidths in the order of 20%, challenging for both the linear processing chain and the frequency reference generator. In classical LC loaded stages bandwidth trades with gain making them unsuitable for wide band amplifiers at millimeter-waves where the available device gain is relatively low. In this work, we exploit inter-stage coupling realizing higher order filters where wider bandwidth is achieved at the expense of in-band gain ripple only. The receiver adopts a sliding IF architecture employing an integer-N type-II synthesizer, with a three state phase frequency detector charge pump combination, a switched tuned LC VCO followed by a low power wide range divider chain. By judicious choice of charge pump current and filter components integrated phase noise, critical for signal constellation integrity at high rate, is kept low. This paper inspects the inter-stage coupling technique, providing design formulas, and discusses the design of each receiver block. Experiments performed on 65 nm prototypes provide: 6.5 dB maximum noise figure over >;13 GHz bandwidth, -22.5 dBc integrated phase noise while consuming 84 mW.

Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations

Transmission lines are becoming of common use at mm-wave to implement on-chip functions as impedance matching, filtering and interconnects. Lack of an accurate and fast simulation method is nonetheless evident for transmission lines in scaled CMOS where metal dummies inserted for IC planarization make their physical structure extremely complicate. Although lines are not uniform due to displacement of small dummies, they are still periodic. In this paper, we describe an analytical procedure, leveraging lines periodicity and based on Floquets theorem, in order to derive electromagnetic parameters from simulations. Conventional, slow-wave and shielded CPWs have been realized in a 65 nm CMOS technology. Thanks to the developed method, an optimum line design has been made possible. The lossy CMOS substrate, responsible for a significant performance degradation, can be effectively shielded and achieved performances are comparable with other technologies considered better suited to implement low-loss, high frequency passive components. Shielded CPW lines show attenuation as low as 0.65 dB/mm at 60 GHz, a record in scaled CMOS.

A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators

Multi-Gb/s wireless communications, allocated in the unlicensed spectrum around 60GHz, have been the topic of intense research in the recent past and devices are expected to hit the market shortly. Key aspects behind the increasing interest for technology deployment are the feasibility of the radio in scaled CMOS and the successful demonstration of Gb/s transmissions [1]. Despite the fact that several circuit techniques at mm-Waves have been introduced in the public literature, key aspects of the analog processing tailored to the application requirements need to be addressed. Four channels covering 57GHz to 66GHz are specified [2]. Considering spreads due to process variation, an ultra-wide RF bandwidth of more than ∼12GHz has to be covered with fine sensitivity. In order to allow high-end rate transmissions, the phase noise of the reference signal is extremely stringent. Furthermore, low power consumption is key to enabling multiple transceivers on the same chip.

A 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS

Scaled CMOS proves to be suitable for the design of transceiver ICs at micro- and millimeter-waves. The effort is presently toward compact and low-power solutions in view of integrating several transceivers on the same chip enabling phased array systems. In this paper we present a 24 GHz receiver, based on a subharmonic direct conversion architecture, designed in a 65 nm node. The local oscillator takes advantage of the half frequency operation proving significantly lower power consumption when compared to conventional solutions running at received frequency. Stacked switches for subharmonic down-conversion are passive to save voltage room, current driven and loaded by a transresistance amplifier. Optimum biasing of the switches allows maximizing linearity while saving power in the baseband. The integrated LNA matching network is the bottleneck toward low sensitivities. The LNA design trades-off power consumption, gain and sensitivity. Detailed insights into implementation issues, critical in a single-ended topology where both forward and return signal paths have to be supported, are provided. The chip consumes 78 mW and occupies 1.4 mm2 of active area. Experiments show: 30.5 dB gain, 6.7 dB NF, -13 dBm IIP3.

A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning

A quadrature oscillator employs a transformer-capacitor network as an energy tank. Frequency tuning is done by varying the transformer magnetic field via the ratio of currents in the two windings. Realized prototypes have a 3.2 to 7.3GHz frequency tuning range, a phase noise FOM of 176.5dB at 3.2GHz, 170.5dB at 6.4GHz, and 164dB at 7GHz, all calculated at 10MHz offset, and a phase error of <1.5deg

A multi standard 1.5 to 10Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication

A 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS is presented. It is based on an adaptive 3-tap latch-based DFE data recovery with self-aligning capability and on an early-late digital clock recovery capable of SSC tracking. Extensive digital features allow self-calibration and eye analysis. The macro measures 0.3 mm2 and consumes 140 mA from 1 V at 8.5 Gb/s.

A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS

Performance of standard CMOS implementations has proved sufficient up to 60 GHz range and examples of operating blocks even beyond 60 GHz have been presented. Still, the choice of the receiver architecture entails several peculiar considerations in order to achieve a robust low-power solution. On the other hand, at high frequencies, to save power in both the VCO and dividers, it is desirable to synthesize a reference frequency that is lower than the received frequency. The authors have proposed a half-harmonic 24 GHz direct-conversion I/Q-receiver front-end with integrated multi-phase LO generation in 65 nm CMOS. Experiments show that adequate performance is achieved in a compact (2.1 mm2) low-power (below 100 mW) solution in an ultra- scaled RF CMOS process.

A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies

Silicon photonics platforms are emerging as attractive solutions for low power and cost effective short/medium-reach optical interconnects. To overcome the intrinsic limitations of monolithically integrated photonics with electronics, STMicroelectronics has developed a 3D-compatible silicon photonics platform that implements in the FEOL only optical devices. Photonics Integrated Circuits are made compatible with 3D assembly of Electronic Integrated Circuits through the use of copper pillars. In this paper we present a 25Gbps Opto-Electronic receiver operating at 1310nm wavelength, consisting of an integrated waveguide Germanium photodiode interfaced by means of copper pillars to a 65nm CMOS amplification chain. The receiver demonstrates an Average Optical Power sensitivity at photodiode input, at a BER of 10-12, of -11.9dBm with a PRBS7 input signal, corresponding to a 97μApp TIA input current. The achieved sensitivity is ~6dB better than state-of-the-art monolithically integrated silicon photonics receivers, at comparable TIA and LA power consumption.

22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s

In this scenario, this work presents a complete 25Gb/s silicon photonics electro-optical transmitter front-end comprising an MZM, using carrier depletion P-N junctions and operating at 1310nm wavelength, and a power-efficient CMOS driver. The transmitter optical path is integrated on STMicroelectronics 3Dcompatible silicon-photonics platform (PIC25G), which implements only optical devices in the front-end of line (FEOL) [4]. The electronic IC, realized in 65nm bulk CMOS technology, is 3D-assembled on top of the photonic IC by means of 20μm-diameter copper pillars, minimizing the interconnection parasitic capacitance. This 1310nm 25Gb/s silicon photonics electro-optical transmitter reports error-free operation with wide open optical eye diagrams at a competitive dynamic extinction ratio (ER) of up to 6dB using a depletion-mode MZM.

Insights Into Silicon Photonics Mach–Zehnder-Based Optical Transmitter Architectures

Mach-Zehnder-based modulator architectures lend themselves to the realization of high-data-rate Silicon Photonics transmitters. In this work the challenges set by the integration of such devices on silicon are analyzed in depth. The two main alternative electronic driver architectures, namely multistage and travelling wave, are compared with focus to power efficiency. This is, in fact, a key parameter when considering the stringent requirements of standard module form factors. A 25 Gbps multistage and a 56 Gbps travelling wave modulator have been realized. Each electro-optical transmitter is obtained by the 3D assembly of an electronic IC on top of a photonic IC through copper pillars. STMicroelectronics PIC25G Silicon Photonics platform has been adopted for the fabrication of optical devices, while 65 nm CMOS and 55 nm BiCMOS technologies are exploited to realize the electronic drivers. A 30% better power efficiency compared to Silicon Photonics state-of-the-art at similar data rates and comparable extinction ratio performance has been demonstrated in both cases. Since packaging is also a crucial aspect for Silicon Photonics high volume production, experiments on bare dice as well as on packaged chips are reported.