Gabriele Saucier

Optimized synthesis of concurrently checked controllers

A method for introducing online test facilities in a controller with a very low overhead is presented. This online test consists of detecting illegal paths in the control flow graph. These illegal paths may be due either to permanent faults or to transient errors. The state code flow is compacted through polynomial division. An implicit justifying signature method is applied at the state code level and ensures identical signatures before each join mode of the control flow graph. The signatures are then independent of the path followed previously in the graph, and the comparison to reference data is greatly facilitated. This property is obtained by a state assignment, nearly without area overhead. The controllers can then be checked by signature analysis, either by a built-in monitor or by an external checker. >

A new approach to control flow checking without program modification

An approach to concurrent control flow checking that avoids performance and software compatibility problems while preserving a high error coverage and a low detection latency is proposed. The approach is called watchdog direct processing. Extensions of the basic method, taking into account the characteristics of complex processors, are also considered. The architecture of a watchdog processor based on the proposed method is described. Implementation results are reported for a watchdog designed for the Intel 80386sx microprocessor.<<ETX>>

ASYL: A Rule-Based System for Controller Synthesis

A rule-based approach has been investigated for two items of the synthesis area: the state assignment of controllers and the logic minimization. Local optimization rules defined on a control flowgraph have been defined for the first point. These are expressed as constraints on the codes of the internal variables. An encoding algorithm tries to respect most of these contraints. The results appeared to be very convincing. For the second point, the rules intend to cope with different technological targets and the meta rules intend to express different optimization strategies. The results are less spectacular, especially, of course, for a target where algorithmic solutions exist, but some interesting experiences on the rule-based approach are reported.

Design of microprocessors with built-in on-line test

Control flow checking techniques are discussed. Invariant properties of the control flow can be checked at two different levels: verification of the sequencing in the controller of the microprocessor or verification of the control flow in the application program. Control flow checking has been implemented, at the two levels, in different versions of a 32-b microprocessor designed in a CMOS 1.5- mu technology. Integration of the monitors on silicon is detailed. The silicon overhead due to the different online test devices is precisely discussed. Different versions of this microprocessor have been designed and implemented in order to make real cost comparisons on components with identical functionality but different integrated monitors. Here only the hardware cost of concurrent checking is considered.<<ETX>>

Using cone structures for circuit partitioning into FPGA packages

Circuit designers and high-level synthesis tools have traditionally used circuit hierarchy to partition circuits into packages. However hierarchical partitioning can not be easily performed if hierarchical blocks have too large a size or too many I-Os. This problem becomes more frequent with field-programmable gate arrays (FPGAs) which commonly have small size limits and up to ten times smaller I-O pin limits. An I-O bottleneck often occurs which during circuit partitioning means more required packages and more ordinary signal wires crossing between the packages. More critical timing paths between packages are cut and circuit operational frequencies are drastically reduced. In this paper, two new partitioning algorithms are presented that use cone structures to partition large hierarchical blocks into FPGAs. Cone structures are minimum cut partitioning structures for netlists with low fanout, and clustering structures for partitioning netlists with high fanout. Cone structures also allow for full containment of critical paths. When used with good merging and cutting strategies, results show the cone partitioning algorithms given here produces fewer FPGG partitions than min-cut with good performance.

The Hyeti defect tolerant microprocessor: a practical experiment and its cost-effectiveness analysis

This paper summarizes a practical experiment in designing a defect tolerant microprocessor and presents the underlying principles. Unlike memory integrated circuits, microprocessors have an irregular structure which complicates both the task of incorporating redundancy for defect tolerance in the design and the task of analyzing the resulting yield increase. The main goal of this paper is to present the detailed yield analysis of a defect tolerant microprocessor with an irregular structure which has been successfully fabricated. The approaches employed for achieving the goal of yield enhancement in the data path and the control part of the microprocessor are described first. Then, the yield enhancement due to the incorporated redundancy is analyzed. Finally, some practical and theoretical conclusions are drawn. >

Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs

A synthesis approach for a set of Boolean functions on table-lookup-based field programmable gate arrays is proposed. Synthesis is considered as a global problem and, therefore, includes suitable factorization techniques as well as decomposition methods relying on the factored form. The factorization step looks for lexicographical expressions of Boolean functions. Some trade-offs between a strict input-driven decomposition and a maximal cell filling strategy are presented. The approach is applied to the Xilinx XC3000 and XC4000 series. Decomposition techniques both for area and speed optimization are detailed and their performance is compared to all available performance results. >

Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Microprocessors

This paper focuses on the adaptation of a concurrent control-flow checking technique to pipelined RISC microprocessors. This technique, called embedded signature monitoring (ESM), verifies the validity of the instructions executed by the processor. Numerous ESM schemes have been studied with non pipelined processors but up-to-date machines pose new problems. The instruction pipeline of these processors makes difficult to know which instructions are actually executed among the fetched ones: the pipeline may be flushed when a jlowcontrol instruction is executed or when an exception is taken. A behavioural model is presented for the pipeline of most recent processors. It is used to propose a new simple ESM scheme compatible with these processors. This scheme is experienced on the Motorola MC88100 RISC processor. The design of a signature monitor dedicated to this processor is presented and hardware costs are discussed.

Hierarchical Test Generation Based on Delayed Propagation

A hierarchical test generation method is presented which is based on a functional approach to guide backward and forward propagations. The proposed algorithm permits solving most propagation conflicts by taking advantage of the functionality of the implemented block and avoids costly unnecessary design modifications. It has been implemented and its effectiveness has been proved on a set of datapaths. The formalism and the algorithms are general enough to handle any type of synchronous digital circuit.

Concurrent checking in dedicated controllers

A novel method for introducing online test facilities in a controller with a very low overhead is presented. This online test consists of detecting illegal paths in the control flow graph. These illegal paths may be due to either permanent faults or transient errors. The implementation of the detection facilities relies on a clever choice of the state codes of the controller, which can then be checked by signature analysis by either a built-in monitor or an external checker.<<ETX>>