Chantal Robach

CATA: A Computer-Aided Test Analysis System

The computer-aided test analysis system helps engineers design systems for testability, both in manufacturing and field maintenance situations. CATA provides test program specifications automatically, and supplies both the information paths through the system and a top-down organization of test procedures. CATA can be applied at various levels of description (from behavioral to register transfer) and in various test contexts (e.g., board or system production). As a result, engineers can determine the expected degree of diagnosis resolution in terms of fault-isolable hardware; they will also be guided toward the necessary system modifications. Software procedures for CATA are written in Pascal and supported by a Vax 11-780 computer.

A DFT Architecture for Asynchronous Networks-on-Chip

The networks-on-chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these network architectures. To test the SoCs, the main challenge is to reach into the embedded cores (i.e, the IPs). In this case, the DFT techniques that integrate test architectures into the SoCs to ease the test of these SoCs are really favoured. In this paper, we present a new methodology for testing NoC architectures. A modular, generic, scalable and configurable DFT architecture is developed in order to ease the test of NoC architectures. The target of this test architecture is asynchronous NoC architectures that are implemented in GALS systems. The proposed architecture is therefore named ANoC-TEST and is implemented in QDI asynchronous circuits. In addition, this architecture can be used to test the computing resources of the networked SoCs. Some initial results and conclusions are also given

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.

Inserting scan at the behavioral level

This article presents a method for inserting test logic at the behavioral level of a VHDL design description. The method is easy to use, and in most cases it requires lower area overhead than classical scan insertion methods.

Testability analysis for software components

In this paper, we propose to use the static single assignment form, which was originally proposed for code optimization in compilation techniques, in order to transform software components into a data-flow representation. Thus, hardware testability concepts can be used to analyze the testability of components that are described by C or Ada programs. Such a testability analysis helps designers during the specification phases of their components and testers during the testing phases to evaluate and eventually to modify the design.

Diversified Test Methods for Local Control Units

Two different test methods, specific to two control mechanisms in a logic network are presented. These methods, in fact, correspond to two levels of complexity and therefore to two kinds of hardware realizations. The main considerations will be the following.

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application

Asynchronous design offers an attractive solution to overcome the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the asynchronous NoCs to the market due to a lack of testing methodology and support. This paper first presents the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.

Testability analysis applied to embedded data-flow software

Testability is an important quality factor of software, particularly embedded data-flow software such as avionics software. A lack of testability of such software can badly affect test costs and software dependability. Testability analysis can be used to identify parts of software which are difficult for testing. In this paper, we propose the use of the static single assignment (SSA) form to transform source code generated from data-flow designs into a data-flow representation, and then we describe some algorithms to automatically translate the SSA form into a testability model. Thus, some metrics can be applied to the testability model in order to locate the software parts which induce a weakness of the testability.

Behavioral modeling of WCDMA transceiver with VHDL-AMS language

This article presents the behavioral modeling of a WCDMA transceiver. The model has been developed in VHDL-AMS language. The WCDMA behavioral model is made of RF parameters like gain, impedance, IIP, leakages. The methodology used to develop this model is included in a top-down design flow. The model has been validated by the comparisons between simulation results and measurements on a silicon prototype

Testability Analysis of Data-Flow Software

This paper is about testability analysis for data-flow software. We describe an application of the SATAN method, which allows testability of data-flow designs to be measured, to analyze testability of the source code of critical data-flow software, such as avionics software. We first propose the transformation of the source code generated from data-flow designs into the Static Single Assignment (SSA) form; then we describe the algorithm to automatically translate the SSA form into a testability model. Thus, analyzing the testability model can allow the detection of the software parts which induce a testability weakness.