Gaoming Xu

FPGA Implementation of CORDIC-Based Square Root Operation for Parameter Extraction of Digital Pre-Distortion for Power Amplifiers

Square root operation is a critical operation in the parameter extraction algorithm of the digital pre-distortion for power amplifiers. Accuracy and speed of square root operation are important factors in the digital pre-distortion parameter extraction process. But square root operation is difficult to realize with normal method for achieving high throughput. In this paper, a CORDIC algorithm, which is realized with pipeline structure on FPGA, is introduced to realize the square root operation. The calculation precision can be improved by increasing the iteration numbers, optimizing and selecting the parameters related to iterations. The CORDIC algorithm is implemented in FPGA and can be called through the Nios II Custom Instruction in Altera Stratix II development platform. The validation results demonstrate that the proposed method simplifies the digital pre-distortion parameter extraction algorithm and speeds up the computation.

A GSM-based wireless remote controller

In this paper, the design and implementation of a wireless remote power controller for home automation based on GSM is introduced. The controller can remotely control the power in our homes through TC35 module at anytime and from anywhere. The controller consists of controlling center and remote receiving module. A prototype of the controller is implemented, and the experiment results show that the controller can easily and flexibly control the home appliances.

Generalized Two-Box Cascaded Nonlinear Behavioral Model for Radio Frequency Power Amplifiers With Strong Memory Effects

Accurately modeling the memory effects is critical in modeling and nonlinearity pre-compensation for wideband radio frequency (RF) power amplifiers (PAs) with strong memory effects. In this paper, the memory effects are divided into two categories: lagging memory effect and leading memory effect, which are defined based on the input samples located after and before the current output samples, separately. Considering the above two types of memory effects, a generalized two-box cascaded (GTBC) nonlinear behavioral model for RF PAs with strong memory effects is proposed: one box for a static nonlinearity block that is used to include the strong static nonlinearities and the other box for a dynamic nonlinearity block which is used to predict the mild dynamic nonlinearities. The modeling accuracy of the proposed model, in terms of the normalized mean square error (NMSE) and the memory effect intensity (MEI), is compared to the generalized memory polynomial (GMP), the augmented Hammerstein (AH) and the enhanced Hammerstein (EH) models for a 450-470 MHz Doherty PA with a three-carrier WCMDA input signal and a 895-935 MHz inverse Class-F Doherty PA with a single-carrier FDD-LTE OFDM input signal. The validation demonstrates that the proposed model leads to high-accuracy with fewer modeling coefficients and floating point operations (FLOPs).

Dual-Band Power Amplifier Using Composite Right/Left-Handed Transmission Line

This paper proposes a dual-band power amplifier employing composite right/left-handed transmission line. The two operating frequencies of the power amplifier are achieved by the nonlinear phase slope and other characteristics of CRLH-TL, which can make an arbitrary selection. The operating frequencies are chosen 950MHz and 1900 MHz in this paper. Through the ADS optimum design, the maximum PAE of 64.862% and 61.437% are obtained at 950MHz and 1900MHz, respectively. The output power obtains 45.618dBm and 48.007dBm at the two frequencies. The gain flatness can maintain ±1 in the 900～1000MHz and 1860～1940MHz.

Bias circuit design of RF power amplifiers for TDD systems

In Time Division Duplex(TDD) system, the radio frequency (RF) power amplifier in a repeater is turned on only when it receives RF signal, thus implementing the sub-frame synchronization and the second conversion point of timeslots is important in TDD system. This paper introduce a bias circuit design to realize the control of the RF power amplifier in the down-link through envelop detection of the received RF signal. The experimental results demonstrated that the proposed bias circuit can properly control the operation status of the power amplifier for a TD-SCDMA system.

Switching characteristics of bias circuits of RF power amplifiers for TD-LTE systems

The RF power amplifiers(PAs) for TDD (Time Division Duplex) systems only turn on in the transmission time slots, which can be realized by the switching control circuits in the bias circuits of the RF PAs. The switching status of the switching control circuit is determined by the envelope detection results of the input RF signals of the RF PA. Therefore, the switching speed of the bias circuits is critical for the performance of the TDD PA. In this paper, the switching characteristics of the bias circuits will be discussed. Then a high speed switching control circuit for Doherty power amplifiers for TD-LTE systems is proposed so as to construct a high quality TDD bias circuit. The experimental results demonstrate that the proposed switching control circuit can effectively improve the speed of the switching speed and satisfy the requirements of the RF power amplifiers in a TD-LTE system.

Linearization of HF power amplifiers with digital predistortion techniques

This paper discuss the nonlinearity compensation techniques for the HF power amplifiers. The memory polynomial predistorter is utilized to pre-compensate the static nonlinearity and the memory effects of the HF power amplifier. The verification results for a practical HF power amplifier demonstrate that the memory polynomial predistorter can effectively suppress the spectrum regrowth caused by the dynamic nonlinearity of HF power amplifier.

Optimization design of FPGA-based look-up-tables for linearizing RF power amplifiers

In this paper, a low-cost hardware implementation of a Look-up-Table(LUT) based digital predistorter (DPD) using Field Programmable Gate Array(FPGA) for power amplifier linearization is proposed. The LUT predistoter is implemented in Altera Stratix II DSP Development Board to simulate the inverse model for memoryless wide-band RF power amplifiers. The parameters of the LUT predistoter are identified using a dynamic exponential weighted moving average algorithm. This paper chooses the suitable table which is occupying less hardware resources from different tables by changing address width and word length for optimizing the design of LUT. Linearization performance is tested with a two-carrier wideband Wideband Code Division Multiple Access (WCDMA) signal.

Optimization design of wideband asymmetric Doherty power amplifiers with different LDMOS devices

In this paper, a wideband asymmetric Doherty power amplifier (WADPA), which has different LDMOS devices for the carrier and the peaking power amplifiers(MRF7S19080 and MRF8S19140), is designed with the stepped impedance transformer. The carrier and peaking amplifiers of the proposed Doherty amplifier operates in class-AB (2.76V) and class-C (1.3V) bias conditions, respectively, with a drain voltage of 27 V. By the help of the computer optimum design, the maximum PAE of 65.407% and the maximum output power of 54.953dBm at 1960MHz are obtained. At about 8dB back-off point, the PAE reaches 55.245%. When Pout equals to 47dBm, the wideband asymmetric Doherty power amplifier covers a bandwidth of 180MHz ranging from 1.87GHz to 2.05GHz while the gain flatness is between −0.3dB to 0.3dB, and the PAE of the whole band is more than 50%.