Gary Hong

Characterization of process-induced mobile ions on the data retention in flash memory

Data retention is a major issue that significantly affects the reliability of nonvolatile memory. In this paper, data retention behaviors due to mobile ions are extensively characterized by using several test methods. The source of mobile ions during the sputtering of Ti/TiN layers for forming salicide inside array was identified by secondary ion mass spectroscopy (SIMS) analysis. Different test sequences clearly reveal the data retention caused by mobile ions. Salicide block material that includes silicon nitride effectively blocks the impact of mobile ions. Bitmapping patterns on an array indicate that the amount of charge loss spatially depends on its neighbors high-V/sub th/ cells via the Coulombs r-square field. The spatial effects of neighboring cells on the charge loss are then estimated. Beyond 1.98 /spl mu/m, the charge loss caused by mobile ions of a individual cell becomes unaffected by the V/sub th/ state of its neighboring cells. Plasma charging cells also attract mobile ions. A considerable charge gain, by as much as 0.8 V with a radial distribution on fresh wafer, was observed after a UV-bake test. The interaction between plasma charging effect and mobile ions movement during wafer processing explains this interesting feature.

Enhanced tunneling characteristics of PECVD silicon-rich-oxide (SRO) for the application in low voltage flash EEPROM

High tunneling efficiency is indispensable for the application of low voltage flash EEPROM. In this study the enhanced tunneling characteristics of the thin silicon-rich-oxide (SRO) films deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) as a tunneling injector was first reported. By optimizing the reactant gas ratios of [N/sub 2/O]/[SiH/sub 4/ during SRO deposition, the tunneling voltage of flash EEPROM can be 1/3 lower than that without PECVD SRO films. The significant tunneling efficiency is found to be caused by the micro Si-islands in SRO films. Micro Si-islands in SRO films enhance the electrical field of the tunneling oxide in flash EEPROM. A modified WKB tunneling approximation has been successfully applied to model the SRO tunneling characteristics. The field enhancement factor of SRO is also found to depend on the oxide electrical field, and is proportion to the inverse of oxide electrical field.

Plasma charging and mobile ions on the data retention of 0.25 /spl mu/m flash memory

Charge retention behavior affected by mobile ions and plasma charging, including charge loss and charge gain, are characterized on a flash cell with different test structures. Meanwhile, the V/sub t/ distribution for a cell array structure test (CAST) array is found to be influenced by program bake and erase bake. The amount of charge loss due to mobile ions for a single cell is around 3 V, which is much worse than the case for CAST arrays, being around 0.6 V. A special feature, charge gain, as much as 0.8 V after UV bake, reveals a wafer radial distribution. An interaction of plasma charging and mobile ions during wafer processing explains this interesting feature. Based on such a proposed physical model, the data retention behavior for various test structures can be well explained.

Performance and Reliability Trade-off of Large-Tilted-Angle Implant P-Pocket on Stacked-Gate Memory Devices

In this paper, the effects of large-tilted-angle p-pocket (LAP) implantation on the performance and reliability of stacked-gate memory cell are investigated. The utilization of LAP process achieves the improved programming efficiency and reduced punchthrough susceptibility. The 45° LAP cell featuring a fastest programming speed, however, would not be desirable due to the seriously aggravated read current degradation, drain/read disturbance, and early snap-back breakdown. The cells with 0° and 30° tilted angle are the feasible cells with the moderate programming performance and acceptable reliability constraints. Furthermore, the 0° LAP cell is preferred for the fact that it exhibits the desirable read current than that in 30° cell. Based on the cell performance and reliability consideration, the 0° p-pocket implanted cell is the optimal angle among 0°, 30° and 45° for the future scaling of stacked-gate memory cell.

A New Ultra Low Voltage Silicon-Rich-Oxide (SRO) NAND Cell

Thin silicon-rich-oxide (SRO) film can be an efficient and reliable tunneling injector for the low voltage application in Flash memory cell. To date, no work has been done on the quantitative and microscopical tunneling model for the SRO enhancement behavior. Moreover, no complete investigation on array-level SRO Flash cell have been presented. In this paper, a new low voltage SNAND (SRO NAND) cell is proposed and investigated, especially in term of performance characteristics and reliability issues. Furthermore, a two-dimensional microscopical model for SRO tunneling characteristics is developed to quantitatively explain the tunneling enhancement characteristics for SRO Flash memory cell. Results show that the tunneling model agrees well with the tunneling characteristics of SNAND cell and also provided the insight into tunnel oxide scaling in SNAND cell operation. The erase and program voltage can be reduced from 22 V to 7 V and 12 V with improved erase speed up to 2 orders, respectively. More than 105 endurance cycles are achieved. The feasibility of the SNAND cell is demonstrated.