Chrong-Jung Lin

Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices

High aspect ratio shallow trench using silicon implanted oxide

Stack gate flash memory cell featuring symmetric self aligned contact structures

Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process

Step-shaped floating poly-si gate to improve gate coupling ratio for flash memory application

Vertical stacked gate flash memory device

Tilt-angle ion implant to improve junction breakdown in flash memory application

Method of making the selection gate in a split-gate flash EEPROM cell and its structure

Flash memory cell with vertical channels, and source/drain bus lines

Method for forming vertical channel flash memory cell using P/N junction isolation