Hwi-Huang Chen

Enhanced tunneling characteristics of PECVD silicon-rich-oxide (SRO) for the application in low voltage flash EEPROM

High tunneling efficiency is indispensable for the application of low voltage flash EEPROM. In this study the enhanced tunneling characteristics of the thin silicon-rich-oxide (SRO) films deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) as a tunneling injector was first reported. By optimizing the reactant gas ratios of [N/sub 2/O]/[SiH/sub 4/ during SRO deposition, the tunneling voltage of flash EEPROM can be 1/3 lower than that without PECVD SRO films. The significant tunneling efficiency is found to be caused by the micro Si-islands in SRO films. Micro Si-islands in SRO films enhance the electrical field of the tunneling oxide in flash EEPROM. A modified WKB tunneling approximation has been successfully applied to model the SRO tunneling characteristics. The field enhancement factor of SRO is also found to depend on the oxide electrical field, and is proportion to the inverse of oxide electrical field.

High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in nor -Type Flash Memory

For the first time, a high-performance (τPGM = 200 ns/τERS = 5 ms) cell with superior reliability characteristics is demonstrated in a nor-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate silicon-oxide-nitride-oxide-silicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight VTH distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.

High-Speed Multilevel Wrapped-Select-Gate SONOS Memory Using a Novel Dynamic Threshold Source-Side-Injection (DTSSI) Programming Method

A high programming speed with a low-power-consumption wrapped-select-gate poly-Si-oxide-nitride-oxide-silicon memory is successfully demonstrated using the novel dynamic threshold source-side-injection programming technique. The select gate embedded in such particular memory structure acts like a dynamic MOSFET resulting in programming current (I PGM) that can be enhanced in this DT mode, easily attaining a high programming speed of about 100 ns. It still doubles the memory density by achieving the 2-bit/cell operation with MLC under DT mode.

Physical Mechanism of High-Programming-Efficiency Dynamic-Threshold Source-Side Injection in Wrapped-Select-Gate SONOS for nor-Type Flash Memory

For the first time, a programming mechanism for conventional source-side injection (SSI) (normal mode), substrate-bias enhanced SSI (body mode), and dynamic-threshold SSI (DTSSI) (DT mode) of a wrapped-select-gate SONOS memory is developed with 2-D Poisson equation and hot-electron simulation and programming characteristic measurement for NOR flash memory. Compared with traditional SSI, DTSSI mechanisms are determined in terms of lateral acceleration electric field and programming current (IPGM) in the neutral gap region, resulting in high programming efficiency. Furthermore, the lateral electric field intersects the vertical electric field, indicating that the main charge injection point is from the end edge of the gap region close to the word gate.

A Highly Reliable Multi-level and 2-bit/cell Operation of Wrapped-Select-Gate (WSG) SONOS Memory with Optimized ONO Thickness

High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well Vth distribution is also presented. High program/erase speed (10 us/5 ms) and low programming current (3.5 u/A) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.