Gary Zhang

Dual mode efficiency enhanced linear power amplifiers using a new balanced structure

This paper presents a new balanced architecture to improve the power added efficiency (PAE) of a 3G handset power amplifier without trading-off its stringent linearity requirement. It is modified from the structure of our Switched Load Insensitive Power Amplifier (LIPA®). Power amplifiers using this modified balanced structure retain the main features of the LIPA and provide boosted PAE performance in low and high power mode. The novel balanced structure is implemented into 4×4mm2 power amplifier modules at both CELL and UMTS bands. For the UMTS band at +28dBm in high mode, 44.5% PAE is achieved, while in low mode at +16dBm, 21% PAE is achieved with an ACLR1 of −38dBc using WCDMA modulation. For CELL band at +28dBm in high mode, 43.5% PAE is achieved, while in low mode, 21% PAE is achieved at +16dBm with an ACLR1 of nearly −39dBc. Both PAs maintain good performance under load mismatch conditions due to the nature of the balanced structure.

A high performance Balanced Power Amplifier and Its Integration into a Front-end Module at PCS Band

A novel load insensitive power amplifier (LIPA) with balanced structure is developed for 3G (HSDPA and HSUPA) handset application at PCS band from 1850-1910 MHz. No external regulated voltage and analog voltage supplies are required at high power level and it is compatible with DC-to-DC converters. Digital or analog control may be applied to further improve its PAE at low and middle power levels. This newly featured PA is integrated into a 4x7 mm2 front-end module (FEM) with good performance, especially under load mismatch condition.

Analysis of output power variation under mismatched load in Power Amplifier FEM with directional coupler

Directional couplers are used for output power detection and control in both WCDMA and GSM/EDGE Power Amplifier (PA) Front End Modules (FEM). At high values of load VSWR, delivered power shows significant variations with the phase. Back-of-envelope calculations are used to estimate output power variations. The objective of this analysis is to define a unified platform for understanding the power control mechanism in PA FEM with directional coupler, explain known-best practices and provide insight into minimizing output power variation. It illustrates how a complex load at isolation port of directional coupler is used to compensate certain non-ideal factors in PA FEM. A practical approach to minimize delivered power variations systematically was implemented and verified in a PA FEM design.

FCC-EIRP-aware UWB pulse generator design approach (invited)

This paper reviews a systematic method for design and analysis of high-order Gaussian pulse generators (PG) for carrier-free impulse-radio ultra wideband (IR-UWB) transceivers, which enables to achieve PG performance optimization and FCC effective isotropic radiated power (EIRP) compliance simultaneously. The new FCC-EIRP-aware design method is verified experimentally using Gaussian PG circuits with different derivative orders designed in CMOS.

ESD protection for RF/AMS ICs: Design and optimization

This paper reviews key factors to practical ESD protection design for RF and analog/mixed-signal (AMS) ICs, including general challenges emerging, ESD-RFIC interactions, RF ESD design optimization and prediction, RF ESD design characterization, ESD-RFIC co-design technique, etc. Practical design examples are discussed. It means to provide a systematic and practical design flow for whole-chip ESD protection design optimization and prediction for RF/AMS ICs to ensure 1st Si design success.

Vast-fast low-triggering LTdSCR ESD protection structure for RF ICs in CMOS

This paper reports design of a novel low-parasitic ultra-low-triggering voltage dual-directional LTdSCR ESD protection structure in foundry CMOS. It features programmable low triggering voltage of 4.7∼6V, low discharging resistance of ∼0.77Ω, low leakage of ∼0.1nA, extremely low parasitic capacitance of ∼10fF and ultra fast response of ∼100ps. it achieves ESD protection of ≫7.8kV HBM and ∼500V CDM for a 90µm device. Measurement matches simulation very well. This low-parasitic low-triggering ESD protection structure is suitable for high data rate and low-voltage RF ICs in CMOS.

Nano crossbar electrostatic discharge protection design

We report design and analysis of new nano crossbar based nano phase switching electrostatic discharge (ESD) protection structures. Measurements confirm ESD protection featuring fast response of 100pS, ultra low leakage I<inf>leak</inf>∼0.11pA, varying trigger voltage (V<inf>t1</inf>) and good ESD protection voltage ratio (ESDV)>230V/µm². This non-traditional nano-crossbar ESD protection can be a potential solution for RF and mixed-signal ICs.

Tunable low-voltage dual-directional ESD protection for RFICs

This paper reports a tunable low triggering voltage, dual-directional SCR ESD protection structure in CMOS for RF ICs. A new embedded gate-coupling technique is used to reduce and adjust its triggering voltage. Experiment shows a low discharging resistance of ∼0.26Ω, low leakage current of ∼0.19nA, low parasitic capacitance of ∼150fF and ultra fast response time of ∼100pS. This structure achieves ESD protection of >9.20kV HBM and >500V CDM for a 90µm device. A high ESD protection to Si ratio of ESDV∼8.17V/µm² is obtained for RF IC applications.

Low power 3.1–10.6 GHz IR-UWB transmitter for Gbps wireless communications

This paper reviews and discusses the design of a low-power single-full-band (3.1–10.6 GHz) noncarrier impulse-radio ultra wideband (UWB) transmitter featuring 5th-order Gaussian derivative pulse shaping, integrated BPSK modulation, and 2.5 kV whole-chip ESD (electrostatic discharge) protection. The UWB transmitter design has been implemented in a commercial 0.18 μm CMOS technology with a very small die size of 0.25 mm2. The fabricated chips have demonstrated full functionality, extremely low power consumption of 0.14 pJ/p-mV, and an ultra short pulse width of 394 ps. This ESD-protected UWB transmitter has the potential to support wireless streaming to gigabit per second (Gbps).

Design optimization and modeling of on-chip RF inductors in 0.13µm and 90nm standard CMOS

This paper discusses general procedures for simulation, design optimization, measurement and modeling of accurate and scalable on-chip RF spiral inductors in standard foundry CMOS for industrial applications. Electro-magnetic (EM) solver is used to simulate and optimize design of a library of inductors with various dimensions and specifications aiming to provide accurate and scalable inductors for typical industrial RF IC designs. A two-step de-embedding method is introduced to ensure precise accurate testing results spanning from 0.1nH to 20nH. SPICE inductor parameter extraction based on an improved 2-π circuit model is conducted to generate accurate BSIM device models for RF IC designs. Design examples in 0.13µm and 90nm CMOS are presented.