Gaurav Verma

Ultra-shallow, abrupt, and highly-activated junctions by low-energy ion implantation and laser annealing

With the recent advances in low-energy ion implantation, the challenges for device manufacturers become how to anneal the implant damage and how to electrically activate implanted dopants. Current rapid thermal processes cause undesired dopant diffusion and have a low electrical activation limited by solid solubility. We report on a process that utilizes a pulsed, ultraviolet laser beam to anneal and activate low-energy implanted junctions. Junctions with depths shallower than 35 nm and sheet resistance smaller than 100 /spl Omega//sq are demonstrated. The results indicate an activated dopant concentration higher than 10/sup 21/ cm/sup -3/. The de-activation of the highly-activated dopants in a subsequent thermal process is also studied. The results suggest that boron junctions will not suffer from de-activation and severe dopant diffusion, and phosphorus may be the choice of n-type dopant because it de-activates less than arsenic. Finally, we will discuss advantages of this process to device performance, present the integration issues, and forecast challenges to the ion implantation community if this process is adopted by device manufacturers.

Laser thermal processing for shallow junction and silicide formation

Verdant Technologies is developing Laser Thermal Processing (LTP) as an alternative to rapid thermal annealing (RTA) for ultra-shallow junction and self-aligned silicide contact formation. Although new, the laser-based technology is a strong contender in the area of contact formation because it offers superior technical performance. The control of dopant diffusion and improvement in activation offered by LTP has led to junctions shallower than 35 nm and with sheet resistance lower than 100 (Omega) /square. Titanium silicide has been shown to form on linewidths down through 0.07 micrometer -- effectively extending the useful lifetime of titanium silicide processing. In addition, the laser-based process allows the silicide thickness over source/drain and gate regions, for both cobalt and titanium, to be controlled independently. This has resulted in gate resistivity of 1 (Omega) /square on linewidths down to 0.07 micrometer. In the Verdant approach, laser light is used to heat the silicon through an absorption process, directly driving the doping or silicidation process in a non-equilibrium and area-specific manner. These aspects of the process allow ultra-shallow contact formation with significantly lower electrical resistance in the silicon and silicide.

Laser-Assisted TiSi 2 Formation for ULSI Applications

In this paper, we describe the results of recent work in which TiSi 2 formation on deep-submicron polysilicon gates is achieved using pulsed excimer laser irradiation. Formation of low resistivity titanium suicide on sub-0.1 μm polysilicon lines is confirmed by sheet resistance measurements. High-resolution TEM examination shows exceptionally smooth interface between suicide and heavily-doped silicon substrate. Gate to source/drain bridging is not observed. Analytical techniques including Rutherford backscattering spectroscopy (RBS) and X-ray diffraction (XRD) have been used to characterize the irradiated films. This laser-assisted suicide formation process is a promising technology for extreme submicron MOSFET applications.

Inspection of Integrated Circuit Databases through Reticle and Wafer Simulation: An Integrated Approach to Design for Manufacturing (DFM)

The present approach to Optical Proximity Correction (OPC) verification has evolved from a number of separate inspection strategies. OPC decoration is verified by a design rule or optical rule checker, the reticle is verified by a reticle inspection system, and the final wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with little or no data flowing between them. In this paper, we will report on a new inspection system called DesignScan that connects the data between the various abstraction layers. DesignScan inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window. The simulated images are compared to the desired pattern and defect detection algorithms are applied to determine if any unacceptable variations in the pattern occurs within the nominal process window. The end result is a new paradigm in design verification, moving beyond OPC verification at the design plane to process window verification at the wafer plane where it really matters. We will demonstrate the application of DesignScan to inspect full chip designs that utilized different Resolution Enhancement Technique (RET) and OPC methods. In doing so, we’ll demonstrate that DesignScan can identify the relative strengths and weaknesses of each methodology by highlighting areas of weak process window for each approach. We will present experimental wafer level results to verify the accuracy of the defect predictions.

Applying reconfigurable RET across process window to create more robust manufacturing designs

Optical proximity corrections (OPC) applied to design layouts are targeted for the nominal process condition FoEo that maintains manufacturing throughput and yield. For designs at 130 nm and above, this is usually sufficient to provide the needed resolution enhancement technology (RET) corrections for high-yield manufacturing. However, for sub-100 nm designs, lack of feature fidelity across the process window becomes a significant contributor to yield loss. It becomes critical to simulate across the lithography process window to predict feature behavior over a wide range of focus and exposure (FE) conditions. KLA-Tencors DesignScan tool simulates the performance of a design across the process window and detects any defects which are then flagged for repair. In the conventional OPC flow, correction of defects entails changing the OPC recipe and redecorating the entire layout. Aprios reconfigurable OPC technology allows one to compute more aggressive OPC corrections at the error locations. This reconfigured OPC replaces the original corrections only at the error locations. This allows prior OPC results to be re-used. The halo or boundary areas associated with the stitching of the modified OPC are simulated and verified and the results are converged back into the layout. This allows the designer to start with a nominal OPC design and by applying reconfigurable OPC technology, eliminate printability errors in the process window, expand the process window, resulting in more robust design performance across the process window. This mask design inspection and optimization method improves yield and shortens cycle time to first wafers, thus providing closure for the design to manufacturing loop.

Lithography process window enhancement using integrated design defect detection and fix

We have reported a new paradigm in design database inspection, moving the OPC verification from the design plane to the wafer plane where it really matters. The DesignScanTM system inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window for an entire chip design. The simulated images are compared to the best focus/exposure reference, and defect detection and CD variation and uniformity algorithms are applied to determine if any unacceptable variation in the pattern occurs within the nominal process window. In addition, DesignScan can sort out detected defects based on the severity of defects-their impact to lithography process window. Such sorting provides powerful guide for prioritizing defective patterns for fixing based upon their contribution for process window enlargement. In this paper, we will report on inspection results of DesignScan on a ProMOS test device database with two different OPC models, in particular its ability to sort defects based on their process window impact. The process window can be enlarged by fixing the weakest patterns, which are the limiting patterns of the process window, until the next weakest patterns become the limiting ones. Previously, we have demonstrated conceptually a database design error detection and correction using DesignScan and Aprios reconfigurable OPC technology on a test database through programmed defects. We will demonstrate in this paper the process window enhancements achieved on a customer test database through the fixing of process window limiting patterns using integrated defect detection, defect severity sorting and OPC correction for the first few groups of defects.

Inspection of integrated circuit database through reticle and wafer simulation: the lithography process window performance monitoring

Approaches to verify post-OPC designs for manufacturing have evolved from a number of separate inspection strategies. OPC decorations are verified by design rule or optical rule checkers, the reticle is verified by a reticle inspection system, and the patterned wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with very little data flowing between them. Previously, we reported a new paradigm in design verification, moving the OPC verification from the design plane to the wafer plane where it really matters. The DesignScanTM system inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure calibration window, which can be up to twice as large as the process window. DesignScanTM first simulates the resist images at the nominal conditions (the best focus/exposure-F0E0) and compares them to pre-OPC design to detect unacceptable variations. Then it simulates resist images across the focus-exposure window and compares them to the best focus/exposure reference. Defect detection algorithms are applied to determine if any unacceptable variation in the pattern occurs within the nominal process window. In this paper we will propose a new methodology on process window monitoring for OPC databases using DesignScan and report results for a chip. We will also report newly developed 2D defect detectors: line end shortening (LES) and interlayer overlap (ILO). New applications will be discussed and reported; such as, determination of the reticle target CD specification through process window simulation across a range of target CDs by biasing the post-OPC data by a few nanometers in both directions (+ and -). Pattern dependent reticle CD specifications are possible by identifying the weak structures.