William Waters Volk

Simulation-based Defect Printability Analysis on Alternating Phase Shifting Masks for 193nm Lithography

For alternating aperture phase shift masks (AAPSM) and 193 nm (ArF) lithography, we have simulated defect printability using inspection images and software-based modeling. Masks were fabricated by DuPont Photomasks with programmed defects of known size, phase, and location. Three phase layers were used to generate defect angles 60, 120 and 180 degrees. Simulated wafer prints were performed using Numerical Technologies’ Virtual Stepper System, which takes inspection images as input and models the lithographic process. With inspection images from KLA-Tencor’s SLF27 system, our critical-dimension measurements show good agreement with those from wafers printed on an ASML PAS 5500/900 scanner.

Investigation of smart inspection of critical layer reticles using additional designer data to determine defect significance

With expected implementation of low k1 lithography on 193nm scanners for 65nm node wafer production, high resolution defect inspection will be needed to insure reticle quality and reticle manufacture process monitoring. Reticle cost and reticle defectivity are both increasing with each shrink to the next node. Simultaneously, system on chip (SoC) designs are increasing in which a large area of the exposure field typically contains dummy patterns and other features which are not electrically active. Knowing which defects will electrically impact device yield and performance can improve reticle manufacturing yield and cycle time -- resulting in lower reticle costs. This investigation examines the feasibility of using additional design data layers for die-to-database reticle inspection to determine in real time the relevance of a reticle defect by its location in the device (Smart InspectionTM). The impact to data preparation and inspection throughput is evaluated. The current prototype algorithm is built on the XPA and XPE die-to-database algorithms for chrome-on-glass and EPSM reticles, respectively. The algorithms implement variable sensitivity based on the additional design data regions. During defect review the defects are intelligently binned into the different predetermined design regions. Tests show the new Smart Inspection algorithm provides the capability of using higher than normal sensitivity in critical regions while reducing sensitivity in less critical regions to filter total defect counts and allow for the review of just defects that matter. Performance characterization of a variable sensitivity Smart Inspection algorithm is discussed in addition to the filtering of the total defect count during review to show the defects that matter to device performance. Using seven critical layer production reticles from a system on chip device we examine the applications of Smart Inspection by layer including active, poly, contact, metal and via layers. Data volume for additional data layers show little impact to inspection data prep time. The total area of the reticle where defects do not matter is as high as 70% on some layers. Review capabilities will be examined for various applications such as reviewing defects in the various regions such as SRAM, dummy pattern, and redundant contact/via specified regions. Lastly, the economics of Smart Inspection will be modeled using the collected knowledge of the applications from the production reticle characterized in this investigation.

New die-to-database inspection algorithm for inspection of 90-nm node reticles

The implementation of low k1 193nm lithography for 90nm node IC production brings new challenges to reticle inspection systems. The inspection tools have to deal with new attenuating films, smaller and more complex features, and more aggressive OPC. In addition, low k1 lithography causes the mask error factor (MEEF) to increase, magnifying CD errors. This, in turn, makes reticle defect detection specifications more aggressive. Achieving high sensitivity, low false defect count, for a full plate inspection is a big challenge. Those three (high sensitivity, low false defect count, full plate inspection) are the three “legs” that must support real die-to-database inspection. In order to demonstrate inspection success, all three must be achieved. Without any of them, there is no die-to-database inspection solution. The capabilities described in this paper (the XPE die-to-database algorithm working with the KLA-Tencor TeraStar SLF87 system) were developed precisely because no tool in the industry was capable of meeting all of these requirements. The industry was in urgent need of a die-to-database system that is capable of inspecting reticles for the 90nm node at high sensitivity, with a low false defect count for a full plate inspection. XPE, the new die-to-database inspection algorithm for the TeraStar SLF87 (XPE-87), has been developed for the inspection of 193nm lithography reticles to be used for the 90nm node and beyond. XPE-87 uses new and improved methods for database rendering, defect detection and image contrast adjustment. The algorithm can accommodate the reticle characteritics, inspecting plates with complex features and addvanced Sub-Resolution Assist Features (SRAFs) at high sensitivity and low false defect count. Thanks to enhancements to system hardware and light calibration routines, the algorithm is very effective at inspecting 90 nm node ArF half-tone reticles. XPE-87 has been characterized with 193 nm and 248 nm EPSM versions of Spica, a new programmed defect test reticle. In the presence of complex OPC, results show a substantial improvement in sensitivity compared to previous die-to-database inspection algorithms. The new algorithm has also been used to inspect a variety of 193nmEPSM, 248 EPSM and chrome on glass production reticles. The results show significant improvement for the inspection of 90 nm node half-tone reticles including plates with SRAFs. Simulations were performed to verify the XPE-87 potential for defect detection. Evaluating changes in signal profile due to the presence of defects, a comparison was performed between the aerial profile of the XPE-87 at UV inspection aerial image and the wafer print aerial image at 193 nm. The results, show a larger signal for defects in small lines.

Investigation of reticle defect formation at DUV lithography

Defect formation on advanced photomasks used for DUV lithography has introduced new challenges at low k1 processes industry wide. Especially at 193-nm scanner exposure, the mask pattern surface, pellicle film and the enclosed space between the pellicle and pattern surface can create a highly reactive environment. This environment can become susceptible to defect growth during repetitive exposure of a mask on DUV lithography systems due to the flow of high energy through the mask. Due to increased number of fields on the wafer, a reticle used at a 300-mm wafer fab receives roughly double the number of exposures without any cool down period, as compared to the reticles in a 200-mm wafer fab. Therefore, 193-nm lithography processes at a 300-mm wafer fab put lithographers and defect engineers into an area of untested mask behavior. During the scope of this investigation, an attenuated phase shift mask (attPSM) was periodically exposed on a 193-nm scanner and the relationship between the number of exposures (i.e., energy passed through the mask during exposures) versus defect growth was developed. Finally, chemical analysis of these defects was performed in order to understand the mechanism of this “growth”.

Formation and detection of subpellicle defects by exposure to DUV system illumination

As DUV lithography becomes more ubiquitous in the manufacture of semiconductors, the importance of detecting mask anomalies that can be attributed to the exposure of mask materials to 248 nm exposure becomes necessary. The requirement to find and eliminate the sources of these types of defects becomes even more important with low k1 lithography. The authors wish to report a new class of defects that can significantly impact mask performance and semiconductor chip manufacturing yields. This paper will discuss the techniques and defect detection systems used to identify the presence of these sub-pellicle (or pellicle-related) defects. Additionally, the mechanism of defect formation and micro-analytical results identifying both the composition and possible sources of the defects will be presented.

Reticle surface contaminants and their relationship to sub-pellicle defect formation

DUV lithography induced sub-pellicle particle formation continues to be a significant problem in semiconductor fabs. We have previously reported on the identification of various defects detected on reticles after extended use. This paper provides a comprehensive evaluation of various molecular contaminants found on the backside surface of a reticle used in high-volume production. Previously all or most of the photo-induced contaminants were detected under the pellicle. This particular contamination is a white “haze” detected by pre-exposure inspection using KLA-Tencor TeraStar STARlight with Un-patterned Reticle Surface Analysis, (URSA). Chemical analysis was done using Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS) and Raman spectroscopy.

Inspection of Integrated Circuit Databases through Reticle and Wafer Simulation: An Integrated Approach to Design for Manufacturing (DFM)

The present approach to Optical Proximity Correction (OPC) verification has evolved from a number of separate inspection strategies. OPC decoration is verified by a design rule or optical rule checker, the reticle is verified by a reticle inspection system, and the final wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with little or no data flowing between them. In this paper, we will report on a new inspection system called DesignScan that connects the data between the various abstraction layers. DesignScan inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window. The simulated images are compared to the desired pattern and defect detection algorithms are applied to determine if any unacceptable variations in the pattern occurs within the nominal process window. The end result is a new paradigm in design verification, moving beyond OPC verification at the design plane to process window verification at the wafer plane where it really matters. We will demonstrate the application of DesignScan to inspect full chip designs that utilized different Resolution Enhancement Technique (RET) and OPC methods. In doing so, we’ll demonstrate that DesignScan can identify the relative strengths and weaknesses of each methodology by highlighting areas of weak process window for each approach. We will present experimental wafer level results to verify the accuracy of the defect predictions.

Multibeam high-resolution die-to-database reticle inspection

A new die-to-database reticle inspection system has been developed to meet the production requirements for 130nm node 4x reticles, as well as, the early inspection requirements for 100nm node 4x reticles. This new system is based on the TeraStarT platform1 developed recently by KLA-Tencor Corporation for high performance die-to-die and STARlightT inspection of 130nm node reticles. The TeraStar platform uses high-NA triple-beam scanning laser optics for high throughput. The platform also includes a new generation of defect detection algorithms and image processing hardware to inspect, with high sensitivity and low false detections, the small linewidths, aggressive OPC, and advanced EPSM 4x reticles characteristic of the 130nm node. The platform further includes the TeraProTM concurrent STARlight and die-to-die inspection mode for exceptional productivity. The necessary database elements have now been developed and added to the TeraStar platform, to give it die-to-database inspection capability. A new data format along with new data preparation, data rendering, and data modeling algorithms have been developed to allow high precision database matching with the optical image for exceptional die-to-database performance. The TeraPro high productivity features of the TeraStar platform have been extended to the die-to-database mode providing the opportunity to use STARlight and die-to-database modes concurrently.

Multibeam high-resolution UV wavelength reticle inspection

A new reticle inspection system with three parallel scanning laser beams for UV imaging for both contamination and pattern inspection has been developed to detect defects on advanced reticles for DUV steppers and low k1 lithography for .13um and extensions to .10um design rules. The development of the new three beam architecture at UV wavelength has significantly increased system throughput while improving the resolution of the imaging optics for inspecting advanced reticles including Halftone, Tri-Tone, and Alternating PSM

Polysilicon gate and polysilicon wire CD/EPE defect detection and classification through process window

As technology advances towards 45nm node and beyond, optical lithography faces increased challenges and resolution enhancement techniques (RET) are imperative for multiple process layers and poly-silicon gate layer in particular. With RET implementation, and optical proximity correction (OPC) techniques, the mask layout deviates further away from design intended layout. For an OPC decorated design database, it is important that before mask making, the OPC is verified that it is design related defects free and provides reasonable process window for a given process to ensure manufacturability. For poly-silicon gate layer, due to tight CD control requirement, the demand for accurate lithography process simulation is even greater. As hyper-NA immersion exposure systems become available, accurate resist image computation considering mask topography effects and partial polarized illumination on poly-silicon gate layers through process window is a necessary. In this work, we will show simulation results of DesignScan on an advanced poly-silicon gate layer using a logic based customer database. Active layer database is used to separate poly-silicon gate regions and poly-silicon wire regions. Sensitive CD and edge placement error (EPE) detectors are used to identify design related defects through the lithography process window. The detector sensitivities can be adjusted based on feature sizes and their geometry (gate of different targets or wires, corners, and line ends). This customization of geometry classification and detector sensitivity is critical to achieve desired through process window inspections. With this capability process window inspections will show how CD/EPE changes as functions of exposure dose and defocus with fast results and efficient review and disposition. Accurate process window assessment using CD variation is obtained.