Gene H. McAllister

A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter

A low-spurious low-power 12-bit 160-MS/s digital to analog converter (DAC) for baseband wireless transmitter is proposed and demonstrated. Degenerated current switches are introduced and benefits of using them are discussed. Mismatch behavior under packaging-induced die stress is also presented. The mobility shift caused by package stress inherited from a thin-die is a dominant source of I/Q mismatch. A 2-channel I/Q DAC core consumes 4 mA with a 1.3/2.6 V dual supply. The 0.13 mm2 I/Q DAC core fabricated in 90-nm digital CMOS process with a highly-integrated digital processor achieves 74 dB SFDR, 55 dB SNDR, and -73 dB THD for a 975 kHz sinusoid at 153.6 MS/s sample rate.

High-Voltage-Tolerant Analog Circuits Design in Deep-Submicrometer CMOS Technologies

Electrical stress-relieved analog circuit design techniques using only baseline devices are presented, 1-to-2 logic level shifter, optional diode insertion, and adaptive biasing scheme are introduced to meet a reliability guideline that ensures sufficient lifetime. The proposed idea was successfully demonstrated with 12-bit I/Q digital-to-analog converter (DAC) and an operational amplifier having a Classs-AB output stage in 65-nm n-well CMOS technology and a high temperature operating life (HTOL) test was performed to evaluate the reliability of the design.

A Pseudodifferential Class AB DAC for Low-Power Wireless Transmitter

A low spurious 12-bit 122.88-MS/s digital-to-analog converter (DAC) enabling a low-power wireless transmit (Tx) chain is proposed and demonstrated. Pseudodifferential class AB DACs are introduced, and the benefits of using them in wireless Tx paths are discussed. The major power savings are achieved in multistage baseband Tx filters and upconversion mixers by using code-dependent linearly scaled dc that is generated from class AB transmit DACs. A two-channel I/Q DAC core consumes 6 mA with a 1.3/2.2-V dual supply. The 0.18-mm2 I/Q DAC core fabricated in a 65-nm digital CMOS process, along with a highly integrated digital baseband processor and radio frequency transceiver, achieves a 73-dB spurious free dynamic range, 61-dB signal-to-noise-plus-distortion ratio, and -70-dB total harmonic distortion for a 990-kHz sinusoid at a 122.88-MS/s sample rate.