Hayg-Taniel Dabag

A Q-Band Amplifier Implemented with Stacked 45-nm CMOS FETs

A stacked FET, single-stage 45-GHz (Q-band) CMOS power amplifier (PA) is presented. The design stacked three FETs to avoid breakdown while allowing a high supply voltage. The IC was implemented in a 45-nm CMOS SOI process. The saturated output power exceeds 18 dBm from a 4-V supply. Integrated shielded coplanar waveguide (CPW) transmission lines as well as metal finger capacitors were used for input and output matching. The amplifier occupies an area of 450x500 im² including pads, while achieving a maximum power-added-efficiency (PAE) above 20%.

Active Millimeter-Wave Phase-Shift Doherty Power Amplifier in 45-nm SOI CMOS

A 45 GHz active phase-shift Doherty PA is proposed and implemented in 45-nm SOI CMOS. The quarter wave-length transmission line at the input of the auxiliary amplifier is replaced by an amplifier, increasing the gain and PAE by more than 1 dB and 5%, while reducing the die area. Use of slow-wave coplanar waveguides (S-CPW) improves the PAE and gain by approximately 3% and 1 dB, and further reduces the die area. Two-stack FET amplifiers are used as the main and auxiliary amplifiers, allowing a supply voltage of 2.5 V and increasing the output power. The active phase-shift Doherty amplifier demonstrates a peak power gain and PAE of 8 dB and 20% at 45 GHz. It occupies 0.45 mm2, and at 6-dB back-off power, the PAE is 21%.

All-Digital Cancellation Technique to Mitigate Receiver Desensitization in Uplink Carrier Aggregation in Cellular Handsets

Future handsets will employ uplink carrier aggregation to increase transmit data rates. This can lead to significant receiver desensitization for a number of LTE band combinations, because of the cross-modulation products created by the nonlinearity of antenna switches and duplexers in the RF front end. To mitigate this effect, an all-digital cancellation algorithm is proposed that relies solely on the digital representation of the signals, a peak covariance search for time alignment, and an adaptive distortion canceller. The recursive least squares (RLS) algorithm is used to find the optimal coefficients for the adaptive filter. Employing the distortion canceller improved the signal-to-interference-plus-noise ratio (SINR) and error-vector-magnitude (EVM) of the desired received signal by up to 20 dB.

Transmission of Signals With Complex Constellations Using Millimeter-Wave Spatially Power-Combined CMOS Power Amplifiers and Digital Predistortion

This paper reports the generation, amplification, and radiation of modulated signals at 45 GHz using a single-chip CMOS power amplifier coupled to a 2 × 2 antenna array. Using digital predistortion, complex constellations were demonstrated for wide modulation bandwidth, which allows high data rates to be transmitted in a spectrally efficient manner. After predistortion, a 98-MS/s 1024-QAM signal with peak-to-average power ratio of 7 dB was demodulated with an error vector magnitude of 1.3%. The measured equivalent isotropically radiated power was 26.2 dBm. The corresponding average RF power produced by the CMOS chip, considering a simulated antenna gain of 12 dB, was 14.2 dBm.

A 45-GHz SiGe HBT amplifier at greater than 25 % efficiency and 30 mW output power

An efficient power amplifier (PA) is demonstrated in a 0.12-µm silicon germanium (SiGe) BiCMOS process at 45 GHz. The amplifier is a single stage common-emitter amplifier (CE). The voltage handling capability of the amplifier is extended by a low impedance biasing network. The amplifier achieves a peak power-added efficiency (PAE) of 25 % at an output power of 13 dBm in linear operation and 31% in class B mode at an output power of 13.3 dBm. The maximum saturated output power Psat is 14.8 dBm, at which the circuit consumes 77 mW. The chip occupies an area of 0.27 mm2 including pads.

All-digital cancellation technique to mitigate self-jamming in uplink carrier aggregation in cellular handsets

Future handsets employing uplink carrier aggregation to increase transmit data rates will experience severe degradation in receiver sensitivity due to intermodulation products created by the nonlinearity of switches and duplexers in the RF front end for a number of LTE band combinations. To maintain the same receiver sensitivity an all-digital cancellation algorithm is proposed that relies solely on the digital representation of the signals, a peak covariance search for time alignment, and a recursive least squares (RLS) adaptive filter. This technique provides up to 20 dB improvement of signal-to-interference-plus-noise ratio (SINR), for 5-MHz LTE signals.

Modeling of Deterministic Output Emissions of Power Amplifiers Into Adjacent Receive Bands

This paper discusses the measurement and modeling of the deterministic components of power amplifier (PA) emissions into neighboring receive (Rx) bands caused by PA nonlinearity, and proposes ways to distinguish these components from stochastic components. A method is presented to determine the orders of nonlinearity that are the principal contributors to the Rx band emissions. A Volterra-based model for their estimation is proposed, along with considerations for estimation accuracy. A criterion based on the matrix condition number for efficient pruning of the Volterra-based models is also presented. The proposed techniques are verified with measurements. The proposed model can be used to gain a deeper understanding of the nonlinearity mechanisms responsible for PA spurious emissions, and offers the possibility of canceling the deterministic components to improve receiver sensitivity.

Linear operation of high-power millimeter-wave stacked-FET PAs in CMOS SOI

Stacked-FET PAs have emerged as a promising circuit technique for high-power CMOS PAs at millimeter-wave bands. Common-source (1-stack) and 3-stack PAs are realized in 45-nm CMOS SOI and compared at 45-GHz. The saturated output power increases from 10 dBm to more than 18 dBm respectively for 1- and 3-stack PAs. Compression and EVM/ACP measurements for QAM modulation are presented to discuss the linearization requirements of millimeter-wave stacked-FET PAs.

High-speed, High-efficiency millimeter-wave transmitters at 45 GHz in CMOS

Millimeter-wave power amplifiers realized in CMOS processes have demonstrated output power and power added efficiency exceeding 20 dBm and 30%, respectively. We describe efforts to achieve high power and high efficiency for mm-wave transmitters and linearize mm-wave PAs in fineline CMOS processes. We will present novel circuit approaches based on Doherty amplifiers and digital pre-distortion of high-power mm-wave CMOS PA to demonstrate low error-vector magnitude (EVM).