Geoffrey Choh-Fei Yeap

Sub-100 nm nMOSFETs with direct tunneling thermal, nitrous and nitric oxides

Performance and reliability of sub-100 nm gate length devices using a dual gate and shallow trench isolated CMOS technology were investigated. Ultra-thin direct tunneling (DT) thermal, nitrous and nitric oxides as thin as 1.3 nm are used. Only N-MOS device results are reported here. The ultra thin LPT gate oxides are produced by a furnace oxidation with a dilute oxygen flow. Nitrous and nitric oxides are formed respectively by N/sub 2/O and NO treatments. The sub-100 nm gate length is realized by a resist trimming technique combined with deep ultraviolet lithography. For the 90 nm gate length (CD SEM) MOSFET with 2.2 nm physical thickness (TEM) of nitrous oxide on the source/drain (S/D) area produced here, the poly profile is almost vertical and the poly gate etch has high selectivity to avoid S/D gate oxide pitting, even with oxide thickness down to 1.3 nm.

High-k scaling for gate insulators: an insightful study

Gate insulator/stack scaling is arguably one of the most challenging aspects of device scaling. As gate lengths are scaled into the sub-100 nm regime, alternate materials other than SiO2 will be needed to continue device scaling. The SIA roadmap has called for introduction of high-k materials below the 100 nm technology node due to problems with direct tunneling in SiO2. However, introduction of high-k poses many challenges in the process/materials side in CMOS process integration. Also, there are device scaling issues that are equally important. When k is increased beyond a certain level, unforeseen effects come to play. A phenomenon known as fringing-induced barrier lowering (FIBL) increases Ioff and degrades the subthreshold swing of the device. This paper describes this phenomenon, and provides insight into device scaling with high k materials. A host of other tradeoffs, especially those concerning control of Ioff and speed, are examined using 2-D simulator and analytical models. Suggestions to control FIBL are also detailed.

Implications of gate stack scaling in sub-100 nm CMOS speed and reliability

Scaling of CMOS devices is projected to continue down to the deep sub-100 nm regime. The gate stack (dielectrics-silicon interface, gate dielectrics and gate contact) is arguably the most critical part of the MOSFET. It is widely believed that oxide will be replaced by high K dielectrics when dielectric thickness is 1.5 nm or below due to excessive direct tunneling (DT) gate leakage. In this work, the effects of high K dielectrics and their interactions with poly depletion (PD), mobility, gate DT leakage and channel charge in sub-100 nm CMOS performance and reliability were investigated.

Hot-carrier effects in sub-100-nm gate-length N-MOSFETs with thermal and nitrided oxide thickness down to 1.3 nm

Device degradation due to hot-carrier injection in sub-100 nm gate length devices has been investigated. 90 nm gate length (CD SEM) N-MOSFETs with 2.2 nm nitrous oxide (Idsat equals 735 uA/micrometer, Idoff equals 1.1 nA/micrometer Vdd equals 1.5 V) are electrically stressed and measured up to 200,000 seconds. Both VgIsubmax and Vg equals Vd stressing conditions at 1.8, 2.0, 2.2 V, 2.5 V and 2.8 V are performed. Contrary to traditional understanding, Vg equals Vd, i.e. channel hot carrier injection CHCI), stress causes more idlin, Idsat, Vt and Gm degradations. Similar trends are observed in NMOS devices fabricated with 1.6 nm thermal and nitrous oxides as well as 1.3 nm nitric oxides. CHCI being a worst case DC hot carrier stress condition for sub-100 nm devices with ultra- thin gate oxides is a gate-length and stress-voltage dependent phenomenon. For 90 nm NMOS devices, VgIsubmax degradation becomes dominant again when stress voltage is 2.0 V or less. For a set stress voltage, e.g. 2.5 V, VgIsubmax degradation is observed to be dominant for gate length (Leff) larger than 130 nm (90 nm). Negligible device degradation (less than 1%) under high uniform gate field tunneling stress suggests lateral electric field is causing the device degradation and CHCI as the dominant stress mechanism in sub-100 nm N-MOSFETs with direct tunneling oxides. Post-stress sub-threshold swing, charge-pumping and DC-current-voltage characterization suggest that stress-generated interface trap is a major cause of device degradation.

Sub-100-nm and deep sub-100-nm MOS transistor gate patterning

This paper reports experimental results of polysilicon gate patterning for sub-100 nm and deep sub-100 nm (less than 50 nm) MOS technology development. Sub-100 nm and deep sub-100 nm polysilicon gates have been achieved using an aggressive etch bias process combined with deep ultraviolet (DUV) lithography. In this paper, we report results on BARC effect, uniformity and iso/dense bias, etch selectivity, poly profile sensitivity, endcap pullback and metrology issues. We have achieved pitting free etch for ultra thin gate oxides down to 15 A. Deep sub-100 nm (approximately 50 nm) photo resist lines and deep sub-100 nm (less than 50 nm) poly gates with a good profile have been obtained.