Ming-Ren Lin

Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates

Metal gate electrodes with two different work functions, /spl sim/4.5 and /spl sim/4.9 eV for NMOS and PMOS, respectively, were obtained by single-step full silicidation of poly gates. Reduction of polysilicon depletion was /spl sim/0.25 nm. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same T/sub oxinv/ as poly gate.

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.

Strained silicon NMOS with nickel-silicide metal gate

Strained Si NMOS transistors with Lgate down to 35 nm were fabricated using NiSi as a metal gate electrode material for the first time. Compared to poly gate devices, NiSi metal gate devices showed further enhanced performance with good control of short channel effects and no degradation in gate oxide integrity.

Nickel silicide metal gate FDSOI devices with improved gate oxide leakage

Fully depleted SOI (FDSOI) devices with undoped channel require metal gates to achieve correct threshold voltages. We demonstrate metal gate FDSOI devices using NiSi gates with symmetric V/sub t/ for both NMOS and PMOS devices. Metal gates are stable on 2 nm gate oxide and show capacitance equivalent gate oxide thickness (CET) 0.6 nm thinner than poly gates. The gate leakage current is up to two orders of magnitude lower and high mobility is achieved (peak electron mobility 670 cm/sup 2//Vs and 170 cm/sup 2//Vs for holes).

70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)

For the first time, a sub-100 nm gate length CMOS transistor is demonstrated with the source/drain extension implemented by laser thermal process (LTP). Ultra-shallow (<30 nm), abrupt, and highly-doped n/sup +/ and p/sup +/ junctions are formed by low-keV implant and 308 nm XeCl excimer laser anneal. Locally selective melting and recrystallization of silicon under the laser beam results in excellent dopant activation for both As and BF/sub 2/. The impact of the laser anneal process is investigated experimentally for MOS transistor characteristics, poly-depletion effect, channel mobility, poly-Si gate and active junction sheet resistances, silicidation, gate oxide leakage, and junction leakage.

50 nm gate-length CMOS transistor with super-halo: design, process, and reliability

CMOS transistors with a 50 nm physical gate length are demonstrated. Super-halo, implemented by angle-tilted implantation, is utilized to control V/sub th/ roll-off down to a gate length of 40 nm. Super-halo also provides V/sub th/ adjustment as well as a retrograde channel to suppress subsurface body punch-through. 935 /spl mu/A//spl mu/m and 395 /spl mu/A//spl mu/m on-state drive currents were achieved for n- and p-channel MOSFETs, respectively, with a V/sub dd/ of 1.5 V. The I/sub drive//(C/sub ox(inv)/V/sub dd/) figure-of-merit (FOM) of the CMOS devices falls on the trend line extrapolated from existing industrial CMOS technologies. The impacts of super-halo on V/sub th/ roll-off, DIBL, gate overlap Miller capacitance and junction capacitance in a 50 nm MOSFET are investigated. Strong halo can result in drain-to-halo (body) band-to-band tunneling leakage even at room temperature. Degradation of gate oxide leakage and hot-carrier reliability due to large-angle-tilted halo implant are concerns in 50 nm CMOS transistors.

Band offset induced threshold variation in strained-Si nMOSFETs

Due to the offset in the valence band, strained-Si nMOSFETs exhibit a -100 mV threshold shift and 4% degradation of the subthreshold slope per each 10% increase of Ge content in the relaxed SiGe layer. The correlation between the threshold shift and strained layer thickness is investigated based on device simulations. In a certain range of the strained-Si layer thickness, the threshold and subthreshold slope change gradually, posing a concern of larger device parameter variation. A larger threshold distribution is observed in devices fabricated with a strained layer thickness comparable to the depletion depth.

Accurate determination of ultrathin gate oxide thickness and effective polysilicon doping of CMOS devices

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 /spl Aring/) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments.

Performance of 70 nm strained-silicon CMOS devices

An 86% electron mobility improvement and over 20% I/sub dn-sat/ enhancement were demonstrated for a 70 nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained-Si process delivered 95% higher inverter peak-current and a 2.2 ps reduction in ring oscillator delay for the same drive current. Strained and bulk CMOS featured equivalent gate leakage through a 16 /spl Aring/ nitrided oxide, which remained the dominant leakage source despite dislocation-induced junction leakage observed on strained-Si wafers. Self-heating of strained-Si CMOS due to the low thermal conductivity SiGe virtual substrate reduces I/sub dn-sat/ by 7% during DC operation.

Locally strained ultra-thin channel 25nm narrow FDSOI devices with metal gate and mesa isolation

Strained silicon devices offer very high carrier mobility. If we put them on an SOI substrate we also improve short-channel control and junction leakage. In this paper, we present a new approach to introducing strain in very thin silicon layers. NMOS and PMOS CV/I performance of 0.2 ps and 0.3 ps, respectively, is the highest reported. We analyze 3D geometrical effects on stress, mobility, and drive currents using the 3D process and device simulator, Taurus.