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Dive into the research topics where Qi Xiang is active.

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Featured researches published by Qi Xiang.


international integrated reliability workshop | 2002

Polarity dependent reliability of advanced MOSFET using MOCVD nitrided Hf-silicate high-k gate dielectric

John Zhang; Eugene Zhao; Qi Xiang; Jay Chan; J. Jeon; Jung-Suk Goo; Amit P. Marathe; B. Ogle; M.-R. Lin; Kurt Taylor

We report reliability of MOSFETs with MOCVD nitrided Hf-silicate (HfSiON) high-k gate dielectric. HfSiON has shown superior electrical characteristics, such as low leakage relative to SiO/sub 2/ and high mobility compared to other high-k gate dielectrics. SILC is found to be comparable to SiO/sub 2/ and better than Hf-silicate without nitridation. TDDB and BTI reveal significant difference between inversion and accumulation mode. Polarity-dependent charge trapping and defect generation are observed and attributed to asymmetric band diagram as well as dissimilar charging processes in two stress modes. Trap-assisted tunneling is evidenced by its strong temperature dependence. Charge pumping tests indicate higher interface density compared to SiO/sub 2//Si. The Weibull slope is determined to be about 3, showing robust wear-out quality of the high-k dielectric.


international conference on advanced thermal processing of semiconductors | 2001

High performance ultra-thin silicon nitride gate dielectrics prepared by in-situ RTCVD techniques

Joong S. Jeon; Qi Xiang; Hyeon S. Kim; Hsing-Huang Tseng; Bob Ogle

Through the characterization of RTCVD process conditions, high performance CMOS devices based on silicon nitride stack gate dielectrics with 40 nm gate length were prepared. In sub 20 /spl Aring/ thick ultra-thin stack gate dielectrics approaching 12 /spl Aring/ of EOT, it was found that HF last cleaned dielectric layer shows slightly higher leakage current as compared to the conventional RCA cleaned dielectric layer. It may be due to thinner dielectric properties on HF last cleaned surfaces. It was also found that annealing with NO, N/sub 2/O and N/sub 2/ modifies the bonding structure of silicon nitride stack layers and significantly improved the properties of ultra-thin stack gate dielectrics.


Archive | 2004

Shallow trench isolation in processes with strained silicon

Haihong Wang; Minh Van Ngo; Qi Xiang; Paul R. Besser; Eric N. Paton; Ming-Ren Lin


Archive | 2004

Shallow trench isolation process for strained silicon processes

Minh-Van Ngo; Qi Xiang; Paul R. Besser; Eric N. Paton; Ming-Ren Lin


Archive | 2004

A method for producing a strained FinFET channel

Qi Xiang; James Pan; Jung-Suk Goo


Archive | 2004

Verfahren zum isolieren flacher gräben in prozessen mit verspanntem silizium.

Paul R. Besser; Ming-Ren Lin; Minh-Van Ngo; Eric N. Paton; Qi Xiang


Archive | 2004

Verfahren zur herstellung eines verspannten finfet-kanals A method for producing a strained FinFET channel

Qi Xiang; James Pan; Jung-Suk Goo


Archive | 2004

Shallow trench isolation process and structure

Qi Xiang; James Pan; Jung-Suk Goo


Archive | 2004

Verfahren zum integrieren von metallen mit verschiedenen austrittsarbeiten zur bildung von cmos-gates mit gatedielektrikum mit hohem k und diesbezügliche struktur

Qi Xiang; Huicai Zhong; Jung-Suk Goo; Allison Holbrook; Joong S. Jeon; George Jonathan Kluth


Archive | 2004

Flache grabenisolation in verfahren mit verspanntem silizium

Paul R. Besser; Ming-Ren Lin; Minh Van Ngo; Eric N. Paton; Haihong Wang; Qi Xiang

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James Pan

Advanced Micro Devices

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