Geoffroy Gosset

Very High Efficiency 13.56 MHz RFID Input Stage Voltage Multipliers Based On Ultra Low Power MOS Diodes

This paper presents an ULP (ultra-low-power) diode based voltage multiplier which is used to convert RF input signal to DC supply voltage. This uses an input signal of 1 V peak to peak and 13.56 MHz frequency and reaches 2 to 3 V at its output with 10 diodes. The IC is implemented in a 2 mum multiple- threshold voltage SOI CMOS technology. The IC outperforms, by a factor larger than 2, classical MOS diodes based voltage multiplier, implemented on the same technology, from the point of view of efficiency (minimum RF input power for given output specifications) and impedance.

Fully-Automated and Portable Design Methodology for Optimal Sizing of Energy-Efficient CMOS Voltage Rectifiers

This paper presents a specific, fully-automated and portable design methodology used to optimize implementations of AC-DC rectifiers using MOS diodes. Output voltage and efficiency are theoretically analyzed taking into account influences of devices DC and AC characteristics, input signal voltages and frequencies as well as load currents, temperatures, backgate voltages and even capacitors and diodes parasitic capacitances. An experimental voltage multiplier is designed in a 1 μm multiple-threshold voltage SOI CMOS technology for ultra low power applications at 13.56 MHz .

A very high efficiency ultra-low-power 13.56MHz voltage rectifier in 150nm SOI CMOS

This paper demonstrates the effectiveness and advantages of ULP (Ultra-Low-Power) MOS diodes vs. standard implementations of a AC-DC voltage multipler in a 150nm multiple-threshold voltage SOI CMOS technology for RFID applications. Introducing a specific design methodology, we compare two 3 stages voltage multipliers, each using one of those diodes types and driving a 1.5µA load. Both architectures use an input signal of 1V peak to peak and 13.56MHz carrier frequency. Efficiency, output voltage, temperature and current load as well as backgate voltage influences are analyzed theoretically and experimentally. The ULP implementation reaches much better output voltage and efficiency than the standard one, by 70% and a factor of 6 respectively under nominal conditions.

Automated Design of a 13.56 MHz 19µW Passive Rectifier With 72% Efficiency Under 10µA load

A three-stage Greinacher rectifier is designed using ultra-low-leakage CMOS diodes and characterized at 13.56 MHz for a 1 Vpp sinusoidal input and a 10 μA load current in 250 nm CMOS bulk technology. The measured dc output voltage is 1.9 V with 72% power conversion efficiency providing a 19 μW output power. This ultra-low-power and high-efficiency ac/dc power converter with 0.13 mm2 chip area can be used with RF energy harvesters to power implantable or wearable biomedical devices in body sensor networks. The automated design optimization methodology using a gradient method and foundry models is presented and discussed. The measured performances are presented for various frequencies, load currents, and input voltages. The robustness against process and temperature variations is studied through temperature measurements and corner simulations.

Design of an Ultra-Low-Power multi-stage AC/DC voltage rectifier and multiplier using a fully-automated and portable design methodology

A fully-automated and portable design methodology has been developed based on an efficient model and a gradients method to optimize an ULP (Ultra Low Power) AC-DC multi-stage rectifier through the overall design window in a practical design time. Innovative ULP diodes featuring two CMOS transistors are modeled and used to reduce leakage. The diode model includes parasitic capacitances, thus taking into account DC and AC behavior for various frequencies and voltage amplitudes. A 3-stage rectifier taking a 1 Vpp input sinusoidal signal at 13.56 MHz and providing a 10 μA load current has been designed in 250 nm bulk CMOS technology with 72% power conversion efficiency and 1.99 V output voltage. Robust design decisions with respect to process corner variations have been reached with this methodology and are also presented.

Ultra-high-efficiency co-integrated photovoltaic energy scavenger

In this paper, we present a SOI CMOS Ultra-Low-Power (ULP) three-stage charge pump designed to interface photovoltaic (PV) cells co-integrated in the SOI substrate and used as a DC power source. Under an irradiance of 100W/m2, 2 PV cells in series provide a 815mV open-circuit voltage and a 21µA short-circuit current. Indoor measurements have been realized connecting them to one charge pump and the obtained output voltages of both the solar cells and charge pump vs. load are discussed. Improvements and perspectives are provided for an irradiance of 500W/m2. Co-integration is realized on a 2µm multiple-threshold voltage SOI CMOS technology for ULP applications.

Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems

In this paper, we describe applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS mixed analog-digital microsystems without compromising the functional performance. The technique is based on a pair of source-connected n- and p-MOS transistors, automatically biasing the stand-by gate-to-source voltage of the nMOSFET at a negative voltage and that of the pMOSFET at a positive level, thereby pushing the off current towards its physical limits. Playing with gate and drain connections, we have created a family of ULP basic blocks: a 2-terminal diode, a 3-terminal transistor and a voltage follower. Using these blocks, we have developed a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high speed performance, highly-efficient power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors.

Disruptive ultra-low-power SOI CMOS circuits towards μW medical sensor implants

In this paper, we propose disruptive circuit design techniques for ultra-low-power (ULP) medical sensor implants. They use unique CMOS blocks to build ULP diodes and transistors that are implemented with ultra-low-Vt devices in 0.15µm fully-depleted SOI CMOS, without process modification. Using these techniques, we propose a highly-efficient power-management unit and a 1.1µW interface for capacitive sensors.

Efficient ultra low power rectification at 13.56 MHz for a 10 µA load current

A 3-stage Greinacher rectifier designed at 13.56 MHz for a 1 Vpp sinusoidal input and a 10 μA load current in 250 nm CMOS bulk technology is characterized. The measured output voltage is 1.923 V DC with an estimated 72% power conversion efficiency. This ultra low power and high efficiency AC/DC power converter with 0.13 mm2 chip area can be used with RF energy harvesters to power implantable or wearable biomedical devices in body sensor networks.

Ultra-low-power analog and digital circuits and microsystems using disruptive ultra-low-leakage design techniques

In this paper, we describe circuits and microsystems applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS analog and digital functions without reducing the functional performance. The technique uses a pair of source-connected n- and p-MOSFETs, implementing an auto-bias of the stand-by gate-to-source voltage of the nMOS transistor at a negative voltage and that of the p-device at a positive level, thereby reducing the off current towards its physical limits. Changing the gate and drain connections, we propose a series of ultra-low-power basic blocks : a 2-terminal diode, a 3-terminal transistor and a voltage follower. These blocks can be combined to yield a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high-speed performance, as well as high-efficiency power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors.