Pierre-Antoine Haddad

Automated Design of a 13.56 MHz 19µW Passive Rectifier With 72% Efficiency Under 10µA load

A three-stage Greinacher rectifier is designed using ultra-low-leakage CMOS diodes and characterized at 13.56 MHz for a 1 Vpp sinusoidal input and a 10 μA load current in 250 nm CMOS bulk technology. The measured dc output voltage is 1.9 V with 72% power conversion efficiency providing a 19 μW output power. This ultra-low-power and high-efficiency ac/dc power converter with 0.13 mm2 chip area can be used with RF energy harvesters to power implantable or wearable biomedical devices in body sensor networks. The automated design optimization methodology using a gradient method and foundry models is presented and discussed. The measured performances are presented for various frequencies, load currents, and input voltages. The robustness against process and temperature variations is studied through temperature measurements and corner simulations.

Design of an Ultra-Low-Power multi-stage AC/DC voltage rectifier and multiplier using a fully-automated and portable design methodology

A fully-automated and portable design methodology has been developed based on an efficient model and a gradients method to optimize an ULP (Ultra Low Power) AC-DC multi-stage rectifier through the overall design window in a practical design time. Innovative ULP diodes featuring two CMOS transistors are modeled and used to reduce leakage. The diode model includes parasitic capacitances, thus taking into account DC and AC behavior for various frequencies and voltage amplitudes. A 3-stage rectifier taking a 1 Vpp input sinusoidal signal at 13.56 MHz and providing a 10 μA load current has been designed in 250 nm bulk CMOS technology with 72% power conversion efficiency and 1.99 V output voltage. Robust design decisions with respect to process corner variations have been reached with this methodology and are also presented.

A Quasi-Static Model of Silicon Substrate Effects in Graphene Field Effect Transistors

Investigations of the fundamental properties of graphene have leveraged the versatility of the CMOS fabrication platform early on by using oxidized semiconductor substrates with a highly doped back gate to behave as a metal gate down to cryogenic temperatures. For future applications at room temperature and co-integration with standard silicon circuits, standard substrates should be considered and modeled. Therefore, we investigate the impact of using standard lightly doped silicon as a back gate by building upon existing drift-diffusion models for the 3-terminal monolayer graphene field effect transistor. Typical measurements of the back-gate transfer characteristics exhibit a kink/plateau around 0 V. This effect is explained by the proposed model and corresponds to a loss of gate control occurring during the formation of the depletion layer in the substrate. The impact is increased at low temperature, for thin oxides or under transient conditions.

Automated design of a 13.56 MHz corner-robust efficient differential drive rectifier for 10 μA load

A portable automated design methodology using a gradient algorithm and foundry models is presented to optimize the cross-coupled and differential-drive rectifier architectures. The impact of threshold voltage, transistor sizing and capacitance are discussed based on the method results and an RC-filter model. Corner robustness is obtained by applying the proposed method in each corner and choosing an intermediate design that maximizes power conversion efficiency over all corners. An 8-stage corner-resistant rectifier is designed at 13.56 MHz for a 1 Vpp sinusoidal input and a 10 μA load current in 250 nm CMOS bulk technology. The simulated output voltage is 2–2.9 V DC with a 50–70% power conversion efficiency providing a 2029 μW output power. This ultra low power and high efficiency AC/DC power converter can be used in inductive RF links as energy harvester to power implantable or wearable biomedical devices in body sensor networks.

Efficient passive energy harvesters at 950 MHz and 2.45 GHz for 100 μW applications in 65 nm CMOS

Two 2-stage rectifiers are designed at 950 MHz and 2.45 GHz in 65 nm CMOS bulk technology to provide a 100 μW output power under 1 V with 79.9% and 76.6% power conversion efficiency, respectively. A portable and automated design methodology is used here based on foundry models. This methodology is extended to optimize both the cross-coupled and differentialdrive rectifier architectures at UHF by using a derivative-free optimization algorithm. Transistor and capacitance sizing are discussed based on the method results and a simple RC-filter model. A first-order matching network is used to simulate the overall conversion efficiency of an energy-harvesting system using a 50 Ω antenna. For 100 μW output power, minimum input powers of −8.84 dBm and −8.56 dBm are simulated at 950 MHz and 2.45 GHz, respectively. These low power and high-efficiency AC/DC power converters can be used as energy harvesters in RF links to power wearable biomedical devices.

Efficient ultra low power rectification at 13.56 MHz for a 10 µA load current

A 3-stage Greinacher rectifier designed at 13.56 MHz for a 1 Vpp sinusoidal input and a 10 μA load current in 250 nm CMOS bulk technology is characterized. The measured output voltage is 1.923 V DC with an estimated 72% power conversion efficiency. This ultra low power and high efficiency AC/DC power converter with 0.13 mm2 chip area can be used with RF energy harvesters to power implantable or wearable biomedical devices in body sensor networks.

Automated layout-integrated sizing of a 2.45 GHz differential-drive rectifier in 28 nm FDSOI CMOS

Rectifiers are considered key analog blocks to power the energy-autonomous wireless applications envisioned by the Internet-of-Things. However, their design routine is still a time-consuming process as the layout step requires human intervention at each iteration of the optimization phase. The layout parasitic effects (e.g. well-proximity effects) introduced by this step can have a non-negligible impact on circuit performances, especially when targeting high-efficiency operation at UHF in the ultra-low power range, where parasitics have a higher impact. In this paper, we propose an automatic sizing and layout integrated methodology, based on commercial digital place and route tools, to optimize the cross-coupled/differential-drive rectifier architecture, including post-layout verification, in an advanced 28nm FDSOI CMOS process. A genetic and a gradient optimization methods are compared to increase the time-efficiency of the methodology. A 3-stage rectifier is optimized, providing 1.17 μW under 1 μΑ load at 2.45 GHz with 68% efficiency.