Georg Tolstoy

Challenges Regarding Parallel Connection of SiC JFETs

State-of-the-art silicon carbide switches have current ratings that are not sufficiently high to be used in high-power converters. It is, therefore, necessary to connect several switches in parallel in order to reach sufficient current capabilities. An investigation of parallel-connected normally ON silicon carbide JFETs is presented in this paper. The device parameters that play the most important role for the parallel connection are the pinch-off voltage, the gate-source reverse breakdown voltage, the spread in the on-state resistances, and the variations in static transfer characteristics of the devices. Moreover, it is experimentally shown that a fifth factor affecting the parallel connection of the devices is the parasitic inductances of the circuit layout. The temperature dependence of the gate-source reverse breakdown voltages is analyzed for two different designs of silicon carbide JFETs. If the spread in the pinch-off and gate-source reverse breakdown voltages is sufficiently large, there might be no possibility for a stable off-state operation of a pair of transistors without forcing one of the gate voltages to exceed the breakdown voltage. A solution to this problem using individual gate circuits for the JFETs is given. The switching performance of two pairs of parallel-connected devices with different combinations of parameters is compared employing two different gate-driver configurations. Three different circuit layouts are considered and the effect of the parasitic inductances is experimentally investigated. It is found that using a single gate circuit for the two mismatched JFETs may improve the switching performance and therefore the distribution of the switching losses significantly. Based on the measured switching losses, it is also clear that regardless of the design of the gate drivers, the lowest total switching losses for the devices are obtained when they are symmetrically placed.

Low-Loss High-Performance Base-Drive Unit for SiC BJTs

Driving a silicon carbide bipolar junction transistor is not a trivial issue, if low drive power consumption and short-switching times are desired. A dual-source base-drive unit with a speed-up capacitor consisting of a low- and a high-voltage source is, therefore, proposed in this paper. As a significant base current is required during the conduction state, the driver power consumption is higher than for other semiconductor switches. In the presented solution, the steady-state base current is provided by a low-voltage source and is optimized for low-power losses. On the contrary, a second source with a higher voltage and speed-up capacitor is used in order to improve the switching performance of the device. The proposed driver has experimentally been compared to other standard driver solutions by using a double-pulse circuit and a 2-kW dc/dc boost converter. Switching times of 20 ns at turn-ON and 35 ns at turn-OFF were recorded. Finally, the efficiency of the converter was determined experimentally at various switching frequencies. From power loss measurements at 100-kHz switching frequency using the proposed driver in a 2-kW dc/dc boost converter, it was found that the efficiency was approximately 99.0%. In the same operating point, the driver power consumption was only 0.08% of the rated power.

High-power modular multilevel converters with SiC JFETs

This paper studies the possibility of building a modular multilevel converter (M2C) using silicon carbide (SiC) switches. The main focus is on a theoretical investigation of the conduction losses of such a converter and a comparison to a corresponding converter with silicon-insulated gate bipolar transistors. Both SiC BJTs and JFETs are considered and compared in order to choose the most suitable technology. One of the submodules of a down-scaled 3 kVA prototype M2C is replaced with a submodule with SiC JFETs without antiparallel diodes. It is shown that the diodeless operation is possible with the JFETs conducting in the negative direction, leaving the possibility to use the body diode during the switching transients. Experimental waveforms for the SiC submodule verify the feasibility during normal steady-state operation. The loss estimation shows that a 300 MW M2C for high-voltage direct current transmission would potentially have an efficiency of approximately 99.8% if equipped with future 3.3 kV 1.2 kA SiC JFETs.

Short-Circuit Protection Circuits for Silicon-Carbide Power Transistors

An experimental analysis of the behavior under short-circuit conditions of three different silicon-carbide (SiC) 1200-V power devices is presented. It is found that all devices take up a substantial voltage, which is favorable for detection of short circuits. A transient thermal device simulation was performed to determine the temperature stress on the die during a short-circuit event, for the SiC MOSFET. It was found that, for reliability reasons, the short-circuit time should be limited to values well below Si IGBT tolerances. Guidelines toward a rugged design for short-circuit protection (SCP) are presented with an emphasis on improving the reliability and availability of the overall system. A SiC device driver with an integrated SCP is presented for each device-type, respectively, where a short-circuit detection is added to a conventional driver design in a simple way. The SCP driver was experimentally evaluated with a detection time of 180 ns. For all devices, short-circuit times well below 1 μs were achieved.

A Discretized Proportional Base Driver for Silicon Carbide Bipolar Junction Transistors

Silicon Carbide Bipolar Junction Transistors require a continuous base current in the on-state. This base current is usually made constant and is corresponding to the maximum collector current and maximum junction temperature that is foreseen in a certain application. In this paper, a discretized proportional base driver is proposed which will reduce, for the right application, the steady-state power consumption of the base driver. The operation of the proposed base driver has been verified experimentally, driving a 1200V/40A SiC BJT in a DC-DC boost converter. In order to determine the potential reduction of the power consumption of the base driver, a case with a dc-dc converter in an ideal electric vehicle driving the new European drive cycle has been investigated. It is found that the steady-state power consumption of the base driver can be reduced by approximately 63%. The total reduction of the driver consumption is 2816 J during the drive cycle, which is slightly more than the total on-state losses for the SiC BJTs used in the converter.

High-Efficiency 312-kVA Three-Phase Inverter Using Parallel Connection of Silicon Carbide MOSFET Power Modules

This paper presents the design process of a 312-kVA three-phase silicon carbide inverter using ten parallel-connected metal-oxide-semiconductor field-effect-transistor power modules in each phase leg. The design processes of the gate-drive circuits with short-circuit protection and power circuit layout are also presented. Measurements in order to evaluate the performance of the gate-drive circuits have been performed using a double-pulse setup. Moreover, electrical and thermal measurements in order to evaluate the transient performance and steady-state operation of the parallel-connected power modules are shown. Experimental results showing proper steady-state operation of the power converter are also presented. Taking into account measured data, an efficiency of approximately 99.3% at the rated power has been measured for the inverter.

Challenges regarding parallel-connection of SiC JFETs

State-of-the-art silicon carbide switches have current ratings that are not sufficiently high to be used in high-power converters. It is, therefore, necessary to connect several switches in parallel in order to reach sufficient current capabilities. An investigation of parallel-connected normally ON silicon carbide JFETs is presented in this paper. The device parameters that play the most important role for the parallel connection are the pinch-off voltage, the gate-source reverse breakdown voltage, the spread in the on-state resistances, and the variations in static transfer characteristics of the devices. Moreover, it is experimentally shown that a fifth factor affecting the parallel connection of the devices is the parasitic inductances of the circuit layout. The temperature dependence of the gate-source reverse breakdown voltages is analyzed for two different designs of silicon carbide JFETs. If the spread in the pinch-off and gate-source reverse breakdown voltages is sufficiently large, there might be no possibility for a stable off-state operation of a pair of transistors without forcing one of the gate voltages to exceed the breakdown voltage. A solution to this problem using individual gate circuits for the JFETs is given. The switching performance of two pairs of parallel-connected devices with different combinations of parameters is compared employing two different gate-driver configurations. Three different circuit layouts are considered and the effect of the parasitic inductances is experimentally investigated. It is found that using a single gate circuit for the two mismatched JFETs may improve the switching performance and therefore the distribution of the switching losses significantly. Based on the measured switching losses, it is also clear that regardless of the design of the gate drivers, the lowest total switching losses for the devices are obtained when they are symmetrically placed.

Comparison of Total Losses of 1.2 kV SiC JFET and BJT in DC-DC Converter Including Gate Driver

The 1.2 kV SiC JFET and BJT devices have been investigated and compared with respect to total losses including the gate driver losses in a DC-DC converter configuration. The buried grid, Normally-on JFET devices with threshold voltage of -50 V and -10V are compared to BJT devices with ideal semiconductor and passivating insulator interface and an interface with surface recombination velocity of 4.5•104 cm/s yielding agreement to the reported experimental current gain values. The conduction losses of both types of devices are independent of the switching frequency while the switching losses are proportional to the switching frequency. The driver losses are proportional to the switching frequency in the JFET case but to a large extent independent of the switching frequency in the BJT case. The passivation of the emitter junction modeled here by surface recombination velocity has a significant impact on conduction losses and gate driver losses in the investigated BJT devices.

Analysis of short-circuit conditions for silicon carbide power transistors and suggestions for protection

An experimental analysis of the behavior under short-circuit conditions of three different Silicon Carbide (SiC) 1200 V power devices is presented. It is found that all devices take up a substantial voltage, which is favorable for detection of short-circuits. A suitable method for short-circuit detection without any comparator is demonstrated. A SiC JFET driver with an integrated short-circuit protection (SCP) is presented where a short-circuit detection is added to a conventional driver design in a simple way. Experimental tests of the SCP driver operating under short-circuit condition and under normal operation are performed successfully.

High-efficiency three-phase inverter with SiC MOSFET power modules for motor-drive applications

This paper presents the design process of a 312 kVA three-phase silicon carbide inverter using ten parallel-connected metal-oxide-semiconductor field-effect-transistor power modules in each phase-leg. The design processes of the gate-drive circuits with short-circuit protection and the power circuit layout are also presented. Electrical measurements in order to evaluate the performance of the gate-drive circuits have been performed using a double-pulse setup. Experimental results showing the electrical performance during steady-state operation of the power converter are also shown. Taking into account measured data, an efficiency of approximately 99.3% at the rated power has been estimated for the inverter.