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Dive into the research topics where Jang-Kwon Lim is active.

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Featured researches published by Jang-Kwon Lim.


energy conversion congress and exposition | 2010

High-power modular multilevel converters with SiC JFETs

Dimosthenis Peftitsis; Georg Tolstoy; Antonios Antonopoulos; Jacek Rabkowski; Jang-Kwon Lim; Mietek Bakowski; Lennart Ängquist; Hans-Peter Nee

This paper studies the possibility of building a modular multilevel converter (M2C) using silicon carbide (SiC) switches. The main focus is on a theoretical investigation of the conduction losses of such a converter and a comparison to a corresponding converter with silicon-insulated gate bipolar transistors. Both SiC BJTs and JFETs are considered and compared in order to choose the most suitable technology. One of the submodules of a down-scaled 3 kVA prototype M2C is replaced with a submodule with SiC JFETs without antiparallel diodes. It is shown that the diodeless operation is possible with the JFETs conducting in the negative direction, leaving the possibility to use the body diode during the switching transients. Experimental waveforms for the SiC submodule verify the feasibility during normal steady-state operation. The loss estimation shows that a 300 MW M2C for high-voltage direct current transmission would potentially have an efficiency of approximately 99.8% if equipped with future 3.3 kV 1.2 kA SiC JFETs.


european conference on power electronics and applications | 2013

Experimental investigations of static and transient current sharing of parallel-connected silicon carbide MOSFETs

Diane-Perle Sadik; Juan Colmenares; Dimosthenis Peftitsis; Jang-Kwon Lim; Jacek Rabkowski; Hans-Peter Nee

An Experimental performance analysis of a parallel connection of two 1200/80 MΩ silicon carbide SiC MOSFETs is presented. Static parallel connection was found to be unproblematic. The switching performance of several pairs of parallel-connected MOSFETs is shown employing a common simple totem-pole driver. Good transient current sharing and high-speed switching waveforms with small oscillations are presented. To conclude this analysis, a dc/dc boost converter using parallel-connected SiC MOSFETs is designed for stepping up a voltage from 50 V to 560 V. It has been found that at high frequencies, a mismatch in switching losses results in thermal unbalance between the devices.


european conference on power electronics and applications | 2015

Investigation of long-term parameter variations of SiC power MOSFETs

Diane-Perle Sadik; Jang-Kwon Lim; Per Ranstad; Hans-Peter Nee

Experimental investigations on the gate-oxide and body-diode reliability of commercially available Silicon Carbide (SiC) MOSFETs from the second generation are performed. The body-diode conduction test is performed with a current density of 50 A/cm2 in order to determine if the body-diode of the MOSFETs is free from bipolar degradation. The second test is stressing the gate-oxide. A negative bias is applied on the gate oxide in order to detect and quantify potential drifts.


IEEE Transactions on Electron Devices | 2015

Design and Characterization of Newly Developed 10 kV 2 A SiC p-i-n Diode for Soft-Switching Industrial Power Supply

Mietek Bakowski; Per Ranstad; Jang-Kwon Lim; Wlodek Kaplan; Sergey A. Reshanov; Adolf Schöner; Florian Giezendanner; Anton Ranstad

10 kV, 2 A SiC p-i-n diodes have been designed and fabricated. The devices feature excellent stability of forward characteristics and robust junction termination with avalanche capability of 1 J. The fabricated diodes have been electrically evaluated with respect to dynamic ON-state voltage, reverse recovery behavior, bipolar stability, and avalanche capability. More than 60% reduction of losses has been demonstrated using newly developed 10-kV p-i-n diodes in a multikilowatt high voltage, high-frequency dc/dc soft-switching converter.


IEEE Transactions on Power Electronics | 2014

Analysis and Experimental Verification of the Influence of Fabrication Process Tolerances and Circuit Parasitics on Transient Current Sharing of Parallel-Connected SiC JFETs

Jang-Kwon Lim; Dimosthenis Peftitsis; Jacek Rabkowski; Mietek Bakowski; Hans-Peter Nee

Operation of parallel-connected 4H-SiC vertical junction field effect transistors (VJFETs) from SemiSouth is modeled using numerical simulations and experimentally verified. The unbalanced current waveforms of parallel-connected VJFETs are investigated with respect to the spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The device structures are reconstructed based on scanning electron microscopy (SEM) analysis, electrical characterization, and device simulations. The doping concentration and profile depth of a p-grid formed by angular implantation are studied as main contributors that influence the variation of the on-state characteristics, and the threshold voltage of the experimental devices. It has been shown elsewhere that similar differences in p-grid also lead to differences in gate-source breakdown voltage. The switching performance of the parallel-connected JFETs is measured using single and double gate drivers in a double-pulse test and compared with simulations. The switched current and voltage waveforms from measurements are reproduced in simulation by introducing the parasitics. From the analysis, it is found that reasonable differences in doping levels and profiles of the p-grid give rise to significant differences in device parameters. However, even with these parameter differences and circuit asymmetries, it is possible to successfully operate parallel-connected VJFETs of this type.


international power electronics and motion control conference | 2012

Experimental comparison of different gate-driver configurations for parallel-connection of normally-on SiC JFETs

Dimosthenis Peftitsis; Jang-Kwon Lim; Jacek Rabkowski; Georg Tolstoy; Hans-Peter Nee

Due to the low current ratings of the currently available silicon carbide (SiC) switches they cannot be employed in high-power converters. Thus, it is necessary to parallel-connect several switches in order to reach higher current ratings. This paper presents an investigation of parallel-connected normally-on SiC junction field effect transistors. There are four crucial parameters affecting the effectiveness of the parallel-connected switches. However, the pinch-off voltage and the reverse breakdown voltage of the gates seem to be the most important parameters which affect the switching performance of the devices. In particular, the spread in these two parameters might affect the stable off-state operation of the switches. The switching performance and the switching losses of a pair of parallel-connected devices having different reverse breakdown voltages of the gates is investigated by employing three different gate-driver configurations. It is experimentally shown that using a single gate-driver circuit the switching performance of the parallel-connected devices is almost identical, while the total switching losses are lower compared to the other two configurations.


Materials Science Forum | 2014

High-Efficiency Power Conversion Using Silicon Carbide Power Electronics

Hans-Peter Nee; Jacek Rabkowski; Dimosthenis Peftitsis; Georg Tolstoy; Juan Colmenares; Diane Sadik; Mietek Bakowski; Jang-Kwon Lim; Antonios Antonopoulos; Lennart Ängquist; Mariusz Zdanowski

The message of this paper is that the silicon carbide power transistors of today are good enough to design converters with efficiencies and switching speeds beyond comparison with corresponding technology in silicon. This is the time to act. Only in the highest power range the devices are missing. Another important step towards high powers is to find new solutions for multi-chip circuit designs that are adapted to the high possible switching speeds of unipolar silicon carbide power transistors.


Symposium on GaN and SiC Power Technologies held during the 220th Meeting of the Electrochemical-Society, OCT 09-14, 2011, Boston, MA | 2011

Merits of Buried Grid Technology for Advanced SiC Device Concepts

Mietek Bakowski; Jang-Kwon Lim; Wlodek Kaplan; Adolf Schöner

Selected examples of the use of buried grid technology for SiC devices are discussed. First example is development of normally-off and normally-on JFETs, Second the development of Schottky barrier ...


Materials Science Forum | 2015

Planarization of Epitaxial SiC Trench Structures by Plasma Ion Etching

Andy Zhang; Sergey A. Reshanov; Adolf Schöner; Wlodek Kaplan; Norbert Kwietniewski; Jang-Kwon Lim; Mietek Bakowski

In this work, we present a planarization concept for epitaxial SiC trench structures involving reactive ion etching (RIE) and inductive coupled plasma (ICP) dry etching. The general idea is to transfer the flat surface from spun-on BCB/photo-resist layers to deposited silicon dioxide and finally to bulk SiC by applying process conditions with the same etch rate for the different materials. In this way several microns of unwanted material can be removed and planar SiC surfaces are obtained. With this method trench structures filled by epitaxial re-growth can be planarized with smooth surfaces and good homogeneity over the wafer. Cost-efficient device manufacturing can be achieved by using standard semiconductor process equipment. This technology makes it possible to manufacture advanced epitaxial SiC material structures for devices such as trench JBS diodes and double-gate trench JFETs.


IMAPS International Conference and Exhibition on High Temperature Electronics, HiTEC 2014 | 2014

High Temperature capable SiC Schottky diodes, based on buried grid design.

Tomas Hjort; Adolf Schöner; Andy Zhang; Mietek Bakowski; Jang-Kwon Lim; Wlodek Kaplan

Electrical characteristics of 4H-SiC Schottky barrier diodes, based on buried grid design are presented. The diodes, rated to 1200V/10A and assembled into high temperature capable TO254 packages, have been tested and studied up to 250°C. Compared to conventional SiC Schottky diodes, Ascatrons buried grid SiC Schottky diode demonstrates several orders of magnitude reduced leakage current at high temperature operation.

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Mietek Bakowski

Royal Institute of Technology

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Hans-Peter Nee

Royal Institute of Technology

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Dimosthenis Peftitsis

Royal Institute of Technology

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Jacek Rabkowski

Warsaw University of Technology

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Georg Tolstoy

Royal Institute of Technology

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Sergey A. Reshanov

University of Erlangen-Nuremberg

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Antonios Antonopoulos

Royal Institute of Technology

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Diane-Perle Sadik

Royal Institute of Technology

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